;   TITLE   BMP.bsf - BMP Script File for Video BIOS
;==============================================================================
; Advance Graphics ROM BIOS
;------------------------------------------------------------------------------
; Copyright (c) Intel Corporation (2000 - 2015).
;
; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS
; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT,
; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES.
; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS.
; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY,
; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER
; WARRANTY.
;
; Intel disclaims all liability, including liability for infringement of
; any proprietary rights, relating to use of the code. No license, express
; or implied, by estoppel or otherwise, to any intellectual property rights
; is granted herein.
;
; File Description:
;   This file is the script file use by the BMP utility which will allow
;   OEM's to edit data and select features on a binary file.
;
;------------------------------------------------------------------------------

;==============================================================================
; Header - Start of BMP Structure Definition
;------------------------------------------------------------------------------
StructDef

Find                                      "BIOS_DATA_BLOCK "

; The following block will determine the reference
; pointer for all table pointer variables.
Find_Ptr_Ref                              "BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data

$BDB_Ver                                  2 bytes     ; BIOS Data Block version number (decimal, e.g.201 = 02.01)
$BDB_Header_Size                          2 bytes     ; BIOS Data Block Header size
$BDB_Size                                 2 bytes     ; BIOS Data Block size

;==============================================================================
; Block 254 - Signon Strings and Other General Data
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size

$Bmp_BIOS_Size                            2 bytes
$BIOS_Type                                1 byte      ; BIOS Type:

$RelStage                                 1 byte      ; Release status

$Chipset                                  1 byte      ; = 25 - Skylake/Kabylake

SKIP                                      2 bit       ; Obsolete
$Integrated_EFP                           1 bit       ; Integrated EFP Support:
$eDP                                      1 bit       ; eDP:
SKIP                                      4 bits
ALIGN

SKIP                                      4 bytes     ; Skip build number string

$Signon                                   155 bytes   ; Signon string
$Copyright                                61 bytes    ; Copyright string

; General Byte Definitions
$bmp_BIOS_CS                              2 bytes     ; BIOS code segment
$bmp_VBIOS_Post_Mode                      1 byte      ; Mode number to set during V BIOS POST
$bmp_BW_Percent                           1 byte      ; Set percentage of total memory BW
SKIP                                      1 byte      ; Pop-up Memory Size
$bmp_Resize_PCI_BIOS                      1 byte      ; BIOS size granularity in 0.5 KB
SKIP                                      1 byte      ; Is the CRT already switched to DDC2

; bmp_Allow_Config
$Allow_Boot_DVI                           1 bit       ; Allow boot DVI even not attach
$Allow_Aspect_Ratio                       1 bit       ; VBIOS aspect ratio for DOS
SKIP                                      6 bits

ALIGN

;==============================================================================
; Block 1 - General Bit Definitions
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size

; bmp_Bits_1
SKIP                                      1 byte      ; Skip bmp_bits_1 completely.
ALIGN

; bmp_Bits_2
$Kvmr_Session_Enable                      1 bit       ; KVMR session enable/boot to fake DVI Display feature
SKIP                                      5 bits
$bmp_Dynamic_CdClock_Supported            1 bit       ; Enable/Disable Dynamic CD Clock select
$Hotplug_Support_Enb                      1 bit       ; Hot Plug support in DOS
ALIGN

; bmp_Bits_3
SKIP                                      2 bits      ; Skip 2 bits
$180_Deg_Rotation_Enable                  1 bit       ; 180 degree rotation enable for LFP in GOP driver.
SKIP                                      5 bits      ; Skip remaining bits.
ALIGN

$bmp_Legacy_Monitor_Detect                1 bit       ; Reserved/Obsolete
SKIP                                      7 bits      ; Reserved bits
ALIGN

; Int_Displays_Support
SKIP                                      3 bits
$DP_SSC_Enb                               1 bit       ; DP SSC Enable bit
SKIP                                      1 bit       ; Obsolete/Reserved from SKL/KBL
$DP_SSC_Dongle_Enb                        1 bit       ; DP SSC dongle Enable/Disable
SKIP                                      2 bits      ; Reserved
ALIGN

;==============================================================================
; Block 253 - PRD Boot Algorithm Table
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size

SKIP                                      1 byte      ; Displays attached field is relevant in VBIOS only
$ChildDevice1Primary                      1 byte      ; Primary
$ChildDevice1Secondary                    1 byte      ; Secondary
SKIP                                      1 byte
$ChildDevice2Primary                      1 byte
$ChildDevice2Secondary                    1 byte
SKIP                                      1 byte
$ChildDevice3Primary                      1 byte
$ChildDevice3Secondary                    1 byte
SKIP                                      1 byte
$ChildDevice4Primary                      1 byte
$ChildDevice4Secondary                    1 byte
SKIP                                      1 byte
$ChildDevice5Primary                      1 byte
$ChildDevice5Secondary                    1 byte
SKIP                                      1 byte
$ChildDevice6Primary                      1 byte
$ChildDevice6Secondary                    1 byte
SKIP                                      1 byte
$ChildDevice7Primary                      1 byte
$ChildDevice7Secondary                    1 byte
SKIP                                      1 byte
$ChildDevice8Primary                      1 byte
$ChildDevice8Secondary                    1 byte
SKIP                                      1 byte
$ChildDevice9Primary                      1 byte
$ChildDevice9Secondary                    1 byte
SKIP                                      1 byte
$ChildDevice10Primary                     1 byte
$ChildDevice10Secondary                   1 byte
SKIP                                      1 byte
$ChildDevice11Primary                     1 byte
$ChildDevice11Secondary                   1 byte
SKIP                                      1 byte
$ChildDevice12Primary                     1 byte
$ChildDevice12Secondary                   1 byte
SKIP                                      1 byte
$ChildDevice13Primary                     1 byte
$ChildDevice13Secondary                   1 byte
SKIP                                      1 byte
$ChildDevice14Primary                     1 byte
$ChildDevice14Secondary                   1 byte
SKIP                                      1 byte
$ChildDevice15Primary                     1 byte
$ChildDevice15Secondary                   1 byte
SKIP                                      1 byte
$ChildDevice16Primary                     1 byte
$ChildDevice16Secondary                   1 byte

SKIP                                      2 bytes     ; No of entries

;==============================================================================
; Block 2 - General Data Definitions
;------------------------------------------------------------------------------

SKIP                                      3 bytes     ; Skip block ID and size

; bmp_DDC_GPIO_Pins
SKIP                                      1 byte      ; Obsolete: Was used for CRT DDC GMBUS pin pair

; bmp_DPMS_Bits
SKIP                                      1 byte      ; Skip bmp_dpms_bits completely.

; bmp_Boot_Dev_Bits
SKIP                                      2 bytes     ; Skip Boot display type

$size_ChildStruc                          1 byte

; Internal LFP Data structure
SKIP                                      10 bytes    ; Skip 10 bytes till Flags 0

SKIP                                      1 bit       ; Skip EDID less enable bit used for EFP's
$Int_LFP_Compression_Enable               1 bit       ; Compression enable bit
$Int_LFP_Compression_Method_Select        1 bit       ; Compression method select PPS/CPS
$Int_LFP_Dual_Pipe_Ganged_Enable          1 bit       ; Dual pipe ganged support enable bit for LFP
SKIP                                      4 bits      ; Skip remaining bits of Flags 0
ALIGN

$Int_LFP_Compression_Struct_Index         4 bits      ; Compression structure index in Block 55
SKIP                                      4 bits      ; Skip remaining bits
ALIGN

$Int_LFP_Slave_Dvo_Port                   1 byte      ; Slave DVO port for LFP display.

SKIP                                      3 bytes     ; Skip reserved_1 and add-in offset fields
$Int_eDP_Port                             1 byte      ; eDP port select
SKIP                                      6 bytes     ; Skip remaining Data structure
SKIP                                      1 bit
$LFP_Lane_Reversal                        1 bit       ; Port Reversal
SKIP                                      1 bit       ; LSPCON bit skipped for LFP
$LFP_IBoost_Enable                        1 bit       ; IBoost enable/disable for LFP.
SKIP                                      1 bit       ; HPD inversion bit for BXT.
SKIP                                      3 bits      ; Reserved
SKIP                                      1 byte
$Int_LFP_AUX_Channel                      1 byte      ; eDP AUX channel
SKIP                                      11 bytes    ; Skip 11 bytes
$Int_LFP_Dp_Boost_Magnitude               4 bits      ; eDP IBoost magnitude level
SKIP                                      4 bits      ; Skip HDMI IBoost magnitude level field for LFP struct

; Internal EFP (HDMI/DP) Data structure
; Device 1
SKIP                                      2 bytes     ; Skip Device Handle
$Int_EFP1_Type                            2 bytes     ; Device type
SKIP                                      1 byte      ; I2C Speed
$Int_EFP1_OnBoard_Pre_emphasis            3 bits      ; Set DisplayPort pre-emphasis level for onboard Redriver
$Int_EFP1_OnBoard_Voltage_swing           3 bits      ; Set DisplayPort voltage swing level for onboard Redriver
$Int_EFP1_OnBoard_Redriver_Present        1 bit       ; Set if onboard Redriver is present
SKIP                                      1 bit       ; Reserved
ALIGN
$Int_EFP1_Dock_Pre_emphasis               3 bits      ; Set DisplayPort Redriver pre-emphasis level for dock Redriver
$Int_EFP1_Dock_Voltage_swing              3 bits      ; Set DisplayPort Redriver voltage swing level for dock Redriver
$Int_EFP1_Dock_Redriver_Present           1 bit       ; Set if dock Redriver is present
SKIP                                      1 bit       ; Reserved
ALIGN
$Int_EFP1_HDMI_LS_Type                    5 bits      ; HDMI Level shifter configuration
$Int_EFP1_HDMI_Maximum_Data_Rate          3 bits      ; HDMI maximum data rate
ALIGN
SKIP                                      2 bytes     ; Skip EDIDless DTD offset
$EFP1_EDIDless_en                         1 bit       ; EDIDless enable bit
$EFP1_Compression_Enable                  1 bit       ; Compression enable bit
$EFP1_Compression_Method_Select           1 bit       ; Compression method select PPS/CPS
$EFP1_Dual_Pipe_Ganged_Enable             1 bit       ; EFP1 dual pipe ganged display enable bit
SKIP                                      4 bits      ; Skip remaining bits
ALIGN
$EFP1_Compression_Struct_Index            4 bits      ; Compression structure index in Block 55
SKIP                                      4 bits      ; Reserved bits
ALIGN
$EFP1_Slave_Dvo_Port                      1 byte      ; Slave DVO port number for EFP 1
SKIP                                      1 byte      ; Skip Reserved_1
SKIP                                      2 bytes     ; skip Addin module table offset
$Int_EFP1_Port                            1 byte      ; EFP1 port
SKIP                                      2 bytes     ; Skip I2C bus and slave address
$Int_EFP1_DDC_Pin                         1 byte      ; EFP1 DDC Pin
SKIP                                      3 bytes     ; Skip Timing info pointer and DVO Config
$Int_EFP1_Port_Dockable                   1 bit       ; HDMI/DP Docked Port
$EFP1_Lane_Reversal                       1 bit       ; Port Reversal
$LSPcon1_Options                          1 bit       ; Hdmi2.0 supported options
$Int_EFP1_IBoost_Enable                   1 bit       ; IBoost enable/disable bit
SKIP                                      1 bit       ; HPD inversion bit for BXT.
SKIP                                      3 bits      ; Reserved
ALIGN
SKIP                                      1 byte      ; Obsolete: Was used for EFP compatibility field
$Int_EFP1_AUX_Channel                     1 byte      ; DP AUX channel
SKIP                                      1 byte      ; Obsolete: Was used for Dongle Detect
SKIP                                      6 bytes     ; Skip to end of child structure
$EFP1_USB_C_DongleFeature_Enabled         1 bit       ; USB type C dongle feature enabled
SKIP                                      7 bits      ; Reserved
SKIP                                      3 bytes     ; GPIO resource ID and GPIO number
$Int_EFP1_Dp_Boost_Magnitude              4 bits      ; DP IBoost magnitude level
$Int_EFP1_Hdmi_Boost_Magnitude            4 bits      ; HDMI IBoost magnitude level

; Device 2
SKIP                                      2 bytes     ; Skip Device Handle
$Int_EFP2_Type                            2 bytes     ; Device type
SKIP                                      1 byte      ; I2C Speed
$Int_EFP2_OnBoard_Pre_emphasis            3 bits      ; Set DisplayPort pre-emphasis level for onboard Redriver
$Int_EFP2_OnBoard_Voltage_swing           3 bits      ; Set DisplayPort voltage swing level for onboard Redriver
$Int_EFP2_OnBoard_Redriver_Present        1 bit       ; Set if onboard Redriver is present
SKIP                                      1 bit       ; Reserved
ALIGN
$Int_EFP2_Dock_Pre_emphasis               3 bits      ; Set DisplayPort Redriver pre-emphasis level for dock Redriver
$Int_EFP2_Dock_Voltage_swing              3 bits      ; Set DisplayPort Redriver voltage swing level for dock Redriver
$Int_EFP2_Dock_Redriver_Present           1 bit       ; Set if dock Redriver is present
SKIP                                      1 bit       ; Reserved
ALIGN
$Int_EFP2_HDMI_LS_Type                    5 bits      ; HDMI Level shifter configuration
$Int_EFP2_HDMI_Maximum_Data_Rate          3 bits      ; HDMI maximum data rate
ALIGN
SKIP                                      2 bytes     ; Skip EDIDless DTD offset
$EFP2_EDIDless_en                         1 bit       ; EDIDless enable bit
$EFP2_Compression_Enable                  1 bit       ; Compression enable bit
$EFP2_Compression_Method_Select           1 bit       ; Compression method select PPS/CPS
$EFP2_Dual_Pipe_Ganged_Enable             1 bit       ; EFP2 dual pipe ganged display enable bit
SKIP                                      4 bits      ; Skip remaining bits
ALIGN
$EFP2_Compression_Struct_Index            4 bits      ; Compression structure index in Block 55
SKIP                                      4 bits      ; Reserved bits
ALIGN
$EFP2_Slave_Dvo_Port                      1 byte      ; Slave DVO port number for EFP 2
SKIP                                      1 byte      ; Skip Reserved_1
SKIP                                      2 bytes     ; skip add-in module table offset
$Int_EFP2_Port                            1 byte      ; EFP1 port
SKIP                                      2 bytes     ; Skip I2C bus and slave address
$Int_EFP2_DDC_Pin                         1 byte      ; EFP1 DDC Pin
SKIP                                      3 bytes     ; Timing info pointer and DVO Config
$Int_EFP2_Port_Dockable                   1 bit       ; HDMI/DP Docked Port
$EFP2_Lane_Reversal                       1 bit       ; Port Reversal
$LSPcon2_Options                          1 bit       ; Hdmi2.0 support options
$Int_EFP2_IBoost_Enable                   1 bit       ; IBoost enable/disable bit
SKIP                                      1 bit       ; HPD inversion bit for BXT.
SKIP                                      3 bits      ; Reserved
ALIGN
SKIP                                      1 byte      ; Obsolete: Was used for EFP compatibility field
$Int_EFP2_AUX_Channel                     1 byte      ; DP AUX channel
SKIP                                      1 byte      ; Obsolete: Was used for Dongle Detect
SKIP                                      6 bytes     ; Skip to end of child structure
$EFP2_USB_C_DongleFeature_Enabled         1 bit       ; USB type C dongle feature enabled
SKIP                                      7 bits      ; Reserved
SKIP                                      3 bytes     ; GPIO resource ID and GPIO number
$Int_EFP2_Dp_Boost_Magnitude              4 bits      ; DP IBoost magnitude level
$Int_EFP2_Hdmi_Boost_Magnitude            4 bits      ; HDMI IBoost magnitude level

; Device 3
SKIP                                      2 bytes     ; Skip Device Handle
$Int_EFP3_Type                            2 bytes     ; Device type
SKIP                                      1 byte      ; I2C Speed
$Int_EFP3_OnBoard_Pre_emphasis            3 bits      ; Set DisplayPort pre-emphasis level for onboard Redriver
$Int_EFP3_OnBoard_Voltage_swing           3 bits      ; Set DisplayPort voltage swing level for onboard Redriver
$Int_EFP3_OnBoard_Redriver_Present        1 bit       ; Set if onboard Redriver is present
SKIP                                      1 bit       ; Reserved
ALIGN
$Int_EFP3_Dock_Pre_emphasis               3 bits      ; Set DisplayPort Redriver pre-emphasis level for dock Redriver
$Int_EFP3_Dock_Voltage_swing              3 bits      ; Set DisplayPort Redriver voltage swing level for dock Redriver
$Int_EFP3_Dock_Redriver_Present           1 bit       ; Set if dock Redriver is present
SKIP                                      1 bit       ; Reserved
ALIGN
$Int_EFP3_HDMI_LS_Type                    5 bits      ; HDMI Level shifter configuration
$Int_EFP3_HDMI_Maximum_Data_Rate          3 bits      ; HDMI maximum data rate
ALIGN
SKIP                                      2 bytes     ; Skip EDIDless DTD offset
$EFP3_EDIDless_en                         1 bit       ; EDIDless enable bit
$EFP3_Compression_Enable                  1 bit       ; Compression enable bit
$EFP3_Compression_Method_Select           1 bit       ; Compression method select PPS/CPS
$EFP3_Dual_Pipe_Ganged_Enable             1 bit       ; EFP3 dual pipe ganged display enable bit
SKIP                                      4 bits      ; Skip remaining bits
ALIGN
$EFP3_Compression_Struct_Index            4 bits      ; Compression structure index in Block 55
SKIP                                      4 bits      ; Reserved bits
ALIGN
$EFP3_Slave_Dvo_Port                      1 byte      ; Slave DVO port number for EFP 3
SKIP                                      1 byte      ; Skip Reserved_1
SKIP                                      2 bytes     ; skip add-in module table offset
$Int_EFP3_Port                            1 byte      ; EFP1 port
SKIP                                      2 bytes     ; Skip I2C bus and slave address
$Int_EFP3_DDC_Pin                         1 byte      ; EFP1 DDC Pin
SKIP                                      3 bytes     ; Skip Timing Info Ptr and DVO Config
$Int_EFP3_Port_Dockable                   1 bit       ; HDMI/DP Docked Port
$EFP3_Lane_Reversal                       1 bit       ; Port Reversal
$LSPcon3_Options                          1 bit       ; Hdmi2.0 supported options
$Int_EFP3_IBoost_Enable                   1 bit       ; IBoost enable/disable bit
SKIP                                      1 bit       ; HPD inversion bit for BXT.
SKIP                                      3 bits      ; Reserved
ALIGN
SKIP                                      1 byte      ; Obsolete: Was used for EFP compatibility field
$Int_EFP3_AUX_Channel                     1 byte      ; DP AUX channel
SKIP                                      1 byte      ; Obsolete: Was used for Dongle Detect
SKIP                                      6 bytes     ; Skip to end of child structure
$EFP3_USB_C_DongleFeature_Enabled         1 bit       ; USB type C dongle feature enabled
SKIP                                      7 bits      ; Reserved
SKIP                                      3 bytes     ; GPIO resource ID and GPIO number
$Int_EFP3_Dp_Boost_Magnitude              4 bits      ; DP IBoost magnitude level
$Int_EFP3_Hdmi_Boost_Magnitude            4 bits      ; HDMI IBoost magnitude level

; Device 4
SKIP                                      2 bytes     ; Skip Device Handle
$Int_EFP4_Type                            2 bytes     ; Device type
SKIP                                      1 byte      ; I2C Speed
$Int_EFP4_OnBoard_Pre_emphasis            3 bits      ; Set DisplayPort pre-emphasis level for onboard Redriver
$Int_EFP4_OnBoard_Voltage_swing           3 bits      ; Set DisplayPort voltage swing level for onboard Redriver
$Int_EFP4_OnBoard_Redriver_Present        1 bit       ; Set if onboard Redriver is present
SKIP                                      1 bit       ; Reserved
ALIGN
$Int_EFP4_Dock_Pre_emphasis               3 bits      ; Set DisplayPort Redriver pre-emphasis level for dock Redriver
$Int_EFP4_Dock_Voltage_swing              3 bits      ; Set DisplayPort Redriver voltage swing level for dock Redriver
$Int_EFP4_Dock_Redriver_Present           1 bit       ; Set if dock Redriver is present
SKIP                                      1 bit       ; Reserved
ALIGN
$Int_EFP4_HDMI_LS_Type                    5 bits      ; HDMI Level shifter configuration
$Int_EFP4_HDMI_Maximum_Data_Rate          3 bits      ; HDMI maximum data rate
ALIGN
SKIP                                      2 bytes     ; Skip EDIDless DTD offset
$EFP4_EDIDless_en                         1 bit       ; EDIDless enable bit
$EFP4_Compression_Enable                  1 bit       ; Compression enable bit
$EFP4_Compression_Method_Select           1 bit       ; Compression method select PPS/CPS
$EFP4_Dual_Pipe_Ganged_Enable             1 bit       ; EFP4 dual pipe ganged display enable bit
SKIP                                      4 bits      ; Skip remaining bits
ALIGN
$EFP4_Compression_Struct_Index            4 bits      ; Compression structure index in Block 55
SKIP                                      4 bits      ; Reserved bits
ALIGN
$EFP4_Slave_Dvo_Port                      1 byte      ; Slave DVO port number for EFP 4
SKIP                                      1 byte      ; Skip Reserved_1
SKIP                                      2 bytes     ; skip add-in module table offset
$Int_EFP4_Port                            1 byte      ; EFP1 port
SKIP                                      2 bytes     ; Skip I2C bus and slave address
$Int_EFP4_DDC_Pin                         1 byte      ; EFP1 DDC Pin
SKIP                                      3 bytes     ; Skip Timing Info Ptr and DVO Config
$Int_EFP4_Port_Dockable                   1 bit       ; HDMI/DP Docked Port
$EFP4_Lane_Reversal                       1 bit       ; Port Reversal
$LSPcon4_Options                          1 bit       ; Hdmi2.0 supported options
$Int_EFP4_IBoost_Enable                   1 bit       ; IBoost enable/disable bit
SKIP                                      1 bit       ; HPD inversion bit for BXT.
SKIP                                      3 bits      ; Reserved
ALIGN
SKIP                                      1 byte      ; Obsolete: Was used for EFP compatibility field
$Int_EFP4_AUX_Channel                     1 byte      ; DP AUX channel
SKIP                                      1 byte      ; Obsolete: Was used for Dongle Detect
SKIP                                      6 bytes     ; Skip to end of child structure
$EFP4_USB_C_DongleFeature_Enabled         1 bit       ; USB type C dongle feature enabled
SKIP                                      7 bits      ; Reserved
SKIP                                      3 bytes     ; GPIO resource ID and GPIO number
$Int_EFP4_Dp_Boost_Magnitude              4 bits      ; DP IBoost magnitude level
$Int_EFP4_Hdmi_Boost_Magnitude            4 bits      ; HDMI IBoost magnitude level

SKIP                                      38 bytes    ; Skip device data structure
SKIP                                      38 bytes    ; Skip device data structure
SKIP                                      38 bytes    ; Skip device data structure

;==============================================================================
; Block 3 - Original Display Toggle List
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size

$bmp_Display_Detect                       1 byte      ; Obsolete

;==============================================================================
; Block 252 - Hook Defintions
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size

SKIP                                      18 bytes    ; Skip 18 SBIOS hooks.

; BMP - Pointer tables
$Dev_Boot_Table_Ptr                       2 bytes     ; Start at BMP Boot table
$Dev_Boot_Table_Size                      2 bytes
$Dev_Boot_Table, $Dev_Boot_Table_Ptr, $Dev_Boot_Table_Size, Offset 0 byte

$Dev_Removed_Table_Ptr                    2 bytes     ; Start at Display Configurations Removal table
$Dev_Removed_Table_Size                   2 bytes
$Dev_Removed_Table, $Dev_Removed_Table_Ptr, $Dev_Removed_Table_Size, Offset 0 byte

$MMIO_Boot_Table_Ptr                      2 bytes     ; Start at BMP Boot table
$MMIO_Boot_Table_Size                     2 bytes
$MMIO_Boot_Table, $MMIO_Boot_Table_Ptr, $MMIO_Boot_Table_Size, Offset 0 byte

$SWF_IO_Table_Ptr                         2 bytes     ; Start of IO SWF Table
$SWF_IO_Table_Size                        2 bytes
$SWF_IO_Table, $SWF_IO_Table_Ptr, $SWF_IO_Table_Size, Offset 3 bytes

$SWF_MMIO_Table_Ptr                       2 bytes     ; Start of MMIO SWF Table
$SWF_MMIO_Table_Size                      2 bytes
$SWF_MMIO_Table, $SWF_MMIO_Table_Ptr, $SWF_MMIO_Table_Size, Offset 3 bytes

$Mode_Rem_Table_Ptr                       2 bytes     ; Start at Mode Removal table
$Mode_Rem_Table_Size                      2 bytes
$Mode_Rem_Table, $Mode_Rem_Table_Ptr, $Mode_Rem_Table_Size, Offset 0 byte

$Toggle_List1_Ptr                         2 bytes     ; Start at BMP Boot table
$Toggle_List1_Size                        2 bytes
$Toggle_List1, $Toggle_List1_Ptr, $Toggle_List1_Size, Offset 0 byte

$Toggle_List2_Ptr                         2 bytes     ; Start at BMP Boot table
$Toggle_List2_Size                        2 bytes
$Toggle_List2, $Toggle_List2_Ptr, $Toggle_List2_Size, Offset 0 byte

$Toggle_List3_Ptr                         2 bytes     ; Start at BMP Boot table
$Toggle_List3_Size                        2 bytes
$Toggle_List3, $Toggle_List3_Ptr, $Toggle_List3_Size, Offset 0 byte

$Toggle_List4_Ptr                         2 bytes     ; Start at BMP Boot table
$Toggle_List4_Size                        2 bytes
$Toggle_List4, $Toggle_List4_Ptr, $Toggle_List4_Size, Offset 0 byte

$eDP_Pwr_Seq_01_Ptr                       2 bytes
$eDP_Pwr_Seq_01_Size                      2 bytes
$eDP_Pwr_Seq_01, $eDP_Pwr_Seq_01_Ptr, $eDP_Pwr_Seq_01_Size, Offset 0 bytes
$eDP_Pwr_Seq_02_Ptr                       2 bytes
$eDP_Pwr_Seq_02_Size                      2 bytes
$eDP_Pwr_Seq_02, $eDP_Pwr_Seq_02_Ptr, $eDP_Pwr_Seq_02_Size, Offset 0 bytes
$eDP_Pwr_Seq_03_Ptr                       2 bytes
$eDP_Pwr_Seq_03_Size                      2 bytes
$eDP_Pwr_Seq_03, $eDP_Pwr_Seq_03_Ptr, $eDP_Pwr_Seq_03_Size, Offset 0 bytes
$eDP_Pwr_Seq_04_Ptr                       2 bytes
$eDP_Pwr_Seq_04_Size                      2 bytes
$eDP_Pwr_Seq_04, $eDP_Pwr_Seq_04_Ptr, $eDP_Pwr_Seq_04_Size, Offset 0 bytes
$eDP_Pwr_Seq_05_Ptr                       2 bytes
$eDP_Pwr_Seq_05_Size                      2 bytes
$eDP_Pwr_Seq_05, $eDP_Pwr_Seq_05_Ptr, $eDP_Pwr_Seq_05_Size, Offset 0 bytes
$eDP_Pwr_Seq_06_Ptr                       2 bytes
$eDP_Pwr_Seq_06_Size                      2 bytes
$eDP_Pwr_Seq_06, $eDP_Pwr_Seq_06_Ptr, $eDP_Pwr_Seq_06_Size, Offset 0 bytes
$eDP_Pwr_Seq_07_Ptr                       2 bytes
$eDP_Pwr_Seq_07_Size                      2 bytes
$eDP_Pwr_Seq_07, $eDP_Pwr_Seq_07_Ptr, $eDP_Pwr_Seq_07_Size, Offset 0 bytes
$eDP_Pwr_Seq_08_Ptr                       2 bytes
$eDP_Pwr_Seq_08_Size                      2 bytes
$eDP_Pwr_Seq_08, $eDP_Pwr_Seq_08_Ptr, $eDP_Pwr_Seq_08_Size, Offset 0 bytes
$eDP_Pwr_Seq_09_Ptr                       2 bytes
$eDP_Pwr_Seq_09_Size                      2 bytes
$eDP_Pwr_Seq_09, $eDP_Pwr_Seq_09_Ptr, $eDP_Pwr_Seq_09_Size, Offset 0 bytes
$eDP_Pwr_Seq_10_Ptr                       2 bytes
$eDP_Pwr_Seq_10_Size                      2 bytes
$eDP_Pwr_Seq_10, $eDP_Pwr_Seq_10_Ptr, $eDP_Pwr_Seq_10_Size, Offset 0 bytes
$eDP_Pwr_Seq_11_Ptr                       2 bytes
$eDP_Pwr_Seq_11_Size                      2 bytes
$eDP_Pwr_Seq_11, $eDP_Pwr_Seq_11_Ptr, $eDP_Pwr_Seq_11_Size, Offset 0 bytes
$eDP_Pwr_Seq_12_Ptr                       2 bytes
$eDP_Pwr_Seq_12_Size                      2 bytes
$eDP_Pwr_Seq_12, $eDP_Pwr_Seq_12_Ptr, $eDP_Pwr_Seq_12_Size, Offset 0 bytes
$eDP_Pwr_Seq_13_Ptr                       2 bytes
$eDP_Pwr_Seq_13_Size                      2 bytes
$eDP_Pwr_Seq_13, $eDP_Pwr_Seq_13_Ptr, $eDP_Pwr_Seq_13_Size, Offset 0 bytes
$eDP_Pwr_Seq_14_Ptr                       2 bytes
$eDP_Pwr_Seq_14_Size                      2 bytes
$eDP_Pwr_Seq_14, $eDP_Pwr_Seq_14_Ptr, $eDP_Pwr_Seq_14_Size, Offset 0 bytes
$eDP_Pwr_Seq_15_Ptr                       2 bytes
$eDP_Pwr_Seq_15_Size                      2 bytes
$eDP_Pwr_Seq_15, $eDP_Pwr_Seq_15_Ptr, $eDP_Pwr_Seq_15_Size, Offset 0 bytes
$eDP_Pwr_Seq_16_Ptr                       2 bytes
$eDP_Pwr_Seq_16_Size                      2 bytes
$eDP_Pwr_Seq_16, $eDP_Pwr_Seq_16_Ptr, $eDP_Pwr_Seq_16_Size, Offset 0 bytes

;==============================================================================
; Block 6 - Extended MMIO Register tables
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size
SKIP                                      117 bytes   ; Skip data

;==============================================================================
; Block 7 - IO Software flag register table for initialization
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size
SKIP                                      7 bytes     ; Skip data

;==============================================================================
; Block 8 - MMIO Software flag register table for initialization
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size
SKIP                                      61 bytes    ; Skip data

;==============================================================================
; Block 9 - PSR/SRD feature control block
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size

; Panel #01
$PSR_FullLink_Enable_01                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_01                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_01                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_01               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_01                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_01                   2 bytes     ; TP2/TP3 wake up time in multiples of 100
ALIGN

; Panel #02
$PSR_FullLink_Enable_02                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_02                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_02                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_02               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_02                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_02                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

; Panel #03
$PSR_FullLink_Enable_03                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_03                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_03                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_03               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_03                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_03                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

; Panel #04
$PSR_FullLink_Enable_04                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_04                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_04                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_04               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_04                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_04                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

; Panel #05
$PSR_FullLink_Enable_05                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_05                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_05                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_05               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_05                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_05                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

; Panel #06
$PSR_FullLink_Enable_06                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_06                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_06                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_06               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_06                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_06                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

; Panel #07
$PSR_FullLink_Enable_07                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_07                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_07                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_07               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_07                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_07                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

; Panel #08
$PSR_FullLink_Enable_08                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_08                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_08                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_08               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_08                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_08                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

; Panel #09
$PSR_FullLink_Enable_09                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_09                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_09                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_09               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_09                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_09                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

; Panel #10
$PSR_FullLink_Enable_10                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_10                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_10                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_10               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit
ALIGN

$PSR_TP1_WaitTime_10                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_10                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

; Panel #11
$PSR_FullLink_Enable_11                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_11                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_11                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_11               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_11                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_11                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

; Panel #12
$PSR_FullLink_Enable_12                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_12                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_12                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_12               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_12                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_12                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

; Panel #13
$PSR_FullLink_Enable_13                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_13                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_13                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_13               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_13                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_13                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

; Panel #14
$PSR_FullLink_Enable_14                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_14                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_14                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_14               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_14                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_14                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

; Panel #15
$PSR_FullLink_Enable_15                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_15                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_15                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_15               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_15                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_15                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

; Panel #16
$PSR_FullLink_Enable_16                   1 bit       ; Full link disable
$PSR_Require_AUX2Wakeup_16                1 bit       ; Require AUX to wake up
SKIP                                      6 bits      ; Reserved
ALIGN

$PSR_IdleFrames2Wait_16                   4 bits      ; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_16               3 bits      ; Lines to wait before link standby
SKIP                                      1 bit       ; Reserved
ALIGN

$PSR_TP1_WaitTime_16                      2 bytes     ; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_16                   2 bytes     ; TP2/TP3 wake up time in multiples of 100

;==============================================================================
; Block 10 - Modes Removal Table.
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size
SKIP                                      203 bytes   ; Skip data

;==============================================================================
; Block 12 - Driver default boot display
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size

SKIP                                      1 bit
SKIP                                      1 bit
$Allow_FDOS_Disp_Switch                   1 bit       ; Obsolete
$Hot_Plug_DVO                             1 bit
SKIP                                      1 bit
$Drv_Int15_hook                           1 bit
$DVD_Sprite_Clone                         1 bit       ; Obsolete
$Use_110h_for_LFP                         1 bit
ALIGN

$Driver_Boot_Mode_X                       2 bytes     ; Obsolete
$Driver_Boot_Mode_Y                       2 bytes     ; Obsolete
$Driver_Boot_Mode_BPP                     1 byte      ; Obsolete
$Driver_Boot_Mode_RR                      1 byte      ; Obsolete

; bmp_Ext_Driver_Bits_1
$Enable_LFP_Primary                       1 bit       ; Obsolete
$GTF_Mode_Pruning                         1 bit       ; Obsolete
SKIP                                      4 bits
$Sprite_Display_Assign                    1 bit       ; Sprite Display Assignment for when Overlay is Active in Clone Mode
$CUI_Maintain_Aspect                      1 bit       ; Display "Maintain Aspect Ratio" via CUI
$Preserve_Aspect_Ratio                    1 bit       ; Preserve Aspect Ratio
$SDVO_Device_Power_Down                   1 bit       ; Obsolete
SKIP                                      1 bit       ; Obsolete: Was used for CRT hot plug
$LVDS_Config                              2 bits      ; LVDS configuration
SKIP                                      1 bit       ; Hot plug TV enable/disable
SKIP                                      2 bits      ; Integrated HDMI Configuration
ALIGN

; bmp_Driver_Flags_1
$CUIHotK_Static_Display                   1 bit
$Embedded_Platform                        1 bit
$Disable_DisplayEnum                      1 bit       ; Used in RCR 2262110
SKIP                                      5 bits
ALIGN

$Legacy_Monitor_Max_X                     2 bytes
$Legacy_Monitor_Max_Y                     2 bytes
$Legacy_Monitor_Max_RR                    1 bytes

; bmp_Ext2_Driver_Bits
$Enable_Int_Src_Term                      1 bit       ; Enable Internal Source Termination for HDMI
SKIP                                      7 bits      ; Reserved
ALIGN

$VBT_Customization_Version                1 byte      ; Customization VBT version number

; bmp_Driver_Feature_Flags
$PM_RMPM_Enable                           1 bit       ; Intel® Rapid Memory Power Management (RMPM) Enable/Disable Flag.
$PM_S2DDT_Enable                          1 bit       ; Intel® Smart 2D Display Technology (S2DDT) Enable/Disable Flag.
$PM_DPST_Enable                           1 bit       ; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag.
$PM_BLC_Enable                            1 bit       ; Backlight Control (BLC) Enable/Disable Flag.
$PM_ADB_Enable                            1 bit       ; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag.
$PM_DRRS_Enable                           1 bit       ; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag.
$PM_RS_Enable                             1 bit       ; Graphics Render Standby (RS) Enable/Disable Flag.
$PM_GPMT_Enable                           1 bit       ; Obsolete
$PM_Turbo_Enable                          1 bit       ; Intel Turbo Boost Technology Enable/Disable Flag.
$Panel_Self_Refresh                       1 bit       ; Panel Self refresh feature (PSR)
$Inter_Pixel_Storage                      1 bit       ; Hidden feature.
$Dynamic_FPS_Enable                       1 bit       ; Dynamic Frames per second(DFPS) feature Enable/Disable Flag.
$DMRRS                                    1 bit       ; Dynamic media refresh rate enable/disable
$ADT                                      1 bit       ; Assertive display technology enable/disable
$HPD_Wake                                 1 bit       ; HPD events routing to display driver when system is in S0ix/DC9, enable/disable
$PC_Fields_Enable                         1 bit       ; PC Feature field's validity Flag.
ALIGN

;==============================================================================
; Block 13 - Driver Persistence Algorithm
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size

SKIP                                      3 bytes     ; Skip block data since it is obsolete.

;==============================================================================
; Block 17 - Test Feature
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size

SKIP                                      8 bytes     ; Skip block data

;==============================================================================
; Block 18 - Driver Rotation Configuration
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size

$Rot_Enable                               1 bit       ; Rotation Enable bit
SKIP                                      7 bits
SKIP                                      11 bytes    ; Reserved

;==============================================================================
; Block 20 - OEM Customizable Modes
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip ID

SKIP                                      2 bytes     ; Table Row/Size Data

$OEM_Mode_Flags1                          1 byte
$OEM_Display_Flags1                       1 byte
$OEM_Mode_X1                              2 bytes
$OEM_Mode_Y1                              2 bytes
$OEM_Mode_Color1                          1 byte
$OEM_Mode_RRate1                          1 byte
$OEM_Mode_DTD1                            18 bytes

$OEM_Mode_Flags2                          1 byte
$OEM_Display_Flags2                       1 byte
$OEM_Mode_X2                              2 bytes
$OEM_Mode_Y2                              2 bytes
$OEM_Mode_Color2                          1 byte
$OEM_Mode_RRate2                          1 byte
$OEM_Mode_DTD2                            18 bytes

$OEM_Mode_Flags3                          1 byte
$OEM_Display_Flags3                       1 byte
$OEM_Mode_X3                              2 bytes
$OEM_Mode_Y3                              2 bytes
$OEM_Mode_Color3                          1 byte
$OEM_Mode_RRate3                          1 byte
$OEM_Mode_DTD3                            18 bytes

$OEM_Mode_Flags4                          1 byte
$OEM_Display_Flags4                       1 byte
$OEM_Mode_X4                              2 bytes
$OEM_Mode_Y4                              2 bytes
$OEM_Mode_Color4                          1 byte
$OEM_Mode_RRate4                          1 byte
$OEM_Mode_DTD4                            18 bytes

$OEM_Mode_Flags5                          1 byte
$OEM_Display_Flags5                       1 byte
$OEM_Mode_X5                              2 bytes
$OEM_Mode_Y5                              2 bytes
$OEM_Mode_Color5                          1 byte
$OEM_Mode_RRate5                          1 byte
$OEM_Mode_DTD5                            18 bytes

$OEM_Mode_Flags6                          1 byte
$OEM_Display_Flags6                       1 byte
$OEM_Mode_X6                              2 bytes
$OEM_Mode_Y6                              2 bytes
$OEM_Mode_Color6                          1 byte
$OEM_Mode_RRate6                          1 byte
$OEM_Mode_DTD6                            18 bytes

;==============================================================================
; Block 26 - TV features
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip ID and size

$Under_Over_Scan_Via_YPrPb                2 bits      ; Obsolete
SKIP                                      10 bits
$Under_Over_Scan_Via_DVI                  2 bits      ; Obsolete
$Add_Overscan_Mode                        1 bit       ; Obsolete
$D_Connector                              1 bit       ; Obsolete
ALIGN

;==============================================================================
; Block 27 - eDP Power Sequencing
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size

; Panel #01 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_01                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_01        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_01      2 bytes
$eDP_DataOff_To_PowerOff_Delay_01         2 bytes
$eDP_PowerCycle_Delay_01                  2 bytes

; Panel #02 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_02                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_02        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_02      2 bytes
$eDP_DataOff_To_PowerOff_Delay_02         2 bytes
$eDP_PowerCycle_Delay_02                  2 bytes

; Panel #03 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_03                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_03        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_03      2 bytes
$eDP_DataOff_To_PowerOff_Delay_03         2 bytes
$eDP_PowerCycle_Delay_03                  2 bytes

; Panel #04 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_04                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_04        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_04      2 bytes
$eDP_DataOff_To_PowerOff_Delay_04         2 bytes
$eDP_PowerCycle_Delay_04                  2 bytes

; Panel #05 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_05                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_05        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_05      2 bytes
$eDP_DataOff_To_PowerOff_Delay_05         2 bytes
$eDP_PowerCycle_Delay_05                  2 bytes

; Panel #06 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_06                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_06        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_06      2 bytes
$eDP_DataOff_To_PowerOff_Delay_06         2 bytes
$eDP_PowerCycle_Delay_06                  2 bytes

; Panel #07 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_07                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_07        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_07      2 bytes
$eDP_DataOff_To_PowerOff_Delay_07         2 bytes
$eDP_PowerCycle_Delay_07                  2 bytes

; Panel #08 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_08                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_08        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_08      2 bytes
$eDP_DataOff_To_PowerOff_Delay_08         2 bytes
$eDP_PowerCycle_Delay_08                  2 bytes

; Panel #09 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_09                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_09        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_09      2 bytes
$eDP_DataOff_To_PowerOff_Delay_09         2 bytes
$eDP_PowerCycle_Delay_09                  2 bytes

; Panel #10 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_10                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_10        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_10      2 bytes
$eDP_DataOff_To_PowerOff_Delay_10         2 bytes
$eDP_PowerCycle_Delay_10                  2 bytes

; Panel #11 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_11                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_11        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_11      2 bytes
$eDP_DataOff_To_PowerOff_Delay_11         2 bytes
$eDP_PowerCycle_Delay_11                  2 bytes

; Panel #12 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_12                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_12        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_12      2 bytes
$eDP_DataOff_To_PowerOff_Delay_12         2 bytes
$eDP_PowerCycle_Delay_12                  2 bytes

; Panel #13 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_13                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_13        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_13      2 bytes
$eDP_DataOff_To_PowerOff_Delay_13         2 bytes
$eDP_PowerCycle_Delay_13                  2 bytes

; Panel #14 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_14                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_14        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_14      2 bytes
$eDP_DataOff_To_PowerOff_Delay_14         2 bytes
$eDP_PowerCycle_Delay_14                  2 bytes

; Panel #15 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_15                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_15        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_15      2 bytes
$eDP_DataOff_To_PowerOff_Delay_15         2 bytes
$eDP_PowerCycle_Delay_15                  2 bytes

; Panel #16 Power Sequencing
$eDP_Vcc_To_Hpd_Delay_16                  2 bytes
$eDP_DataOn_To_BkltEnable_Delay_16        2 bytes
$eDP_BkltDisable_To_DataOff_Delay_16      2 bytes
$eDP_DataOff_To_PowerOff_Delay_16         2 bytes
$eDP_PowerCycle_Delay_16                  2 bytes

$eDP_Panel_Color_Depth_01                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_02                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_03                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_04                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_05                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_06                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_07                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_08                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_09                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_10                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_11                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_12                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_13                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_14                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_15                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
$eDP_Panel_Color_Depth_16                 2 bits      ; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp

$eDP_Link_DataRate_01                     4 bits      ; Panel #01 Link Data Rate
$eDP_Link_LaneCount_01                    4 bits      ; Panel #01 Link Lane Count
$eDP_Link_PreEmp_01                       4 bits      ; Panel #01 Link Pre-emphasis
$eDP_Link_Vswing_01                       4 bits      ; Panel #01 Link Voltage Swing

$eDP_Link_DataRate_02                     4 bits      ; Panel #02 Link Data Rate
$eDP_Link_LaneCount_02                    4 bits      ; Panel #02 Link Lane Count
$eDP_Link_PreEmp_02                       4 bits      ; Panel #02 Link Pre-emphasis
$eDP_Link_Vswing_02                       4 bits      ; Panel #02 Link Voltage Swing

$eDP_Link_DataRate_03                     4 bits      ; Panel #03 Link Data Rate
$eDP_Link_LaneCount_03                    4 bits      ; Panel #03 Link Lane Count
$eDP_Link_PreEmp_03                       4 bits      ; Panel #03 Link Pre-emphasis
$eDP_Link_Vswing_03                       4 bits      ; Panel #03 Link Voltage Swing

$eDP_Link_DataRate_04                     4 bits      ; Panel #04 Link Data Rate
$eDP_Link_LaneCount_04                    4 bits      ; Panel #04 Link Lane Count
$eDP_Link_PreEmp_04                       4 bits      ; Panel #04 Link Pre-emphasis
$eDP_Link_Vswing_04                       4 bits      ; Panel #04 Link Voltage Swing

$eDP_Link_DataRate_05                     4 bits      ; Panel #05 Link Data Rate
$eDP_Link_LaneCount_05                    4 bits      ; Panel #05 Link Lane Count
$eDP_Link_PreEmp_05                       4 bits      ; Panel #05 Link Pre-emphasis
$eDP_Link_Vswing_05                       4 bits      ; Panel #05 Link Voltage Swing

$eDP_Link_DataRate_06                     4 bits      ; Panel #06 Link Data Rate
$eDP_Link_LaneCount_06                    4 bits      ; Panel #06 Link Lane Count
$eDP_Link_PreEmp_06                       4 bits      ; Panel #06 Link Pre-emphasis
$eDP_Link_Vswing_06                       4 bits      ; Panel #06 Link Voltage Swing

$eDP_Link_DataRate_07                     4 bits      ; Panel #07 Link Data Rate
$eDP_Link_LaneCount_07                    4 bits      ; Panel #07 Link Lane Count
$eDP_Link_PreEmp_07                       4 bits      ; Panel #07 Link Pre-emphasis
$eDP_Link_Vswing_07                       4 bits      ; Panel #07 Link Voltage Swing

$eDP_Link_DataRate_08                     4 bits      ; Panel #08 Link Data Rate
$eDP_Link_LaneCount_08                    4 bits      ; Panel #08 Link Lane Count
$eDP_Link_PreEmp_08                       4 bits      ; Panel #08 Link Pre-emphasis
$eDP_Link_Vswing_08                       4 bits      ; Panel #08 Link Voltage Swing

$eDP_Link_DataRate_09                     4 bits      ; Panel #09 Link Data Rate
$eDP_Link_LaneCount_09                    4 bits      ; Panel #09 Link Lane Count
$eDP_Link_PreEmp_09                       4 bits      ; Panel #09 Link Pre-emphasis
$eDP_Link_Vswing_09                       4 bits      ; Panel #09 Link Voltage Swing

$eDP_Link_DataRate_10                     4 bits      ; Panel #10 Link Data Rate
$eDP_Link_LaneCount_10                    4 bits      ; Panel #10 Link Lane Count
$eDP_Link_PreEmp_10                       4 bits      ; Panel #10 Link Pre-emphasis
$eDP_Link_Vswing_10                       4 bits      ; Panel #10 Link Voltage Swing

$eDP_Link_DataRate_11                     4 bits      ; Panel #11 Link Data Rate
$eDP_Link_LaneCount_11                    4 bits      ; Panel #11 Link Lane Count
$eDP_Link_PreEmp_11                       4 bits      ; Panel #11 Link Pre-emphasis
$eDP_Link_Vswing_11                       4 bits      ; Panel #11 Link Voltage Swing

$eDP_Link_DataRate_12                     4 bits      ; Panel #12 Link Data Rate
$eDP_Link_LaneCount_12                    4 bits      ; Panel #12 Link Lane Count
$eDP_Link_PreEmp_12                       4 bits      ; Panel #12 Link Pre-emphasis
$eDP_Link_Vswing_12                       4 bits      ; Panel #12 Link Voltage Swing

$eDP_Link_DataRate_13                     4 bits      ; Panel #13 Link Data Rate
$eDP_Link_LaneCount_13                    4 bits      ; Panel #13 Link Lane Count
$eDP_Link_PreEmp_13                       4 bits      ; Panel #13 Link Pre-emphasis
$eDP_Link_Vswing_13                       4 bits      ; Panel #13 Link Voltage Swing

$eDP_Link_DataRate_14                     4 bits      ; Panel #14 Link Data Rate
$eDP_Link_LaneCount_14                    4 bits      ; Panel #14 Link Lane Count
$eDP_Link_PreEmp_14                       4 bits      ; Panel #14 Link Pre-emphasis
$eDP_Link_Vswing_14                       4 bits      ; Panel #14 Link Voltage Swing

$eDP_Link_DataRate_15                     4 bits      ; Panel #15 Link Data Rate
$eDP_Link_LaneCount_15                    4 bits      ; Panel #15 Link Lane Count
$eDP_Link_PreEmp_15                       4 bits      ; Panel #15 Link Pre-emphasis
$eDP_Link_Vswing_15                       4 bits      ; Panel #15 Link Voltage Swing

$eDP_Link_DataRate_16                     4 bits      ; Panel #16 Link Data Rate
$eDP_Link_LaneCount_16                    4 bits      ; Panel #16 Link Lane Count
$eDP_Link_PreEmp_16                       4 bits      ; Panel #16 Link Pre-emphasis
$eDP_Link_Vswing_16                       4 bits      ; Panel #16 Link Voltage Swing

SKIP                                      4 bytes     ; Obsolete: Was used for DRRS MSA Delay.

SKIP                                      2 bytes     ; Obsolete: S3D enable disable VBT bit for 16 panels.

$eDP_T3_Optimization_01                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #01
$eDP_T3_Optimization_02                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #02
$eDP_T3_Optimization_03                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #03
$eDP_T3_Optimization_04                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #04
$eDP_T3_Optimization_05                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #05
$eDP_T3_Optimization_06                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #06
$eDP_T3_Optimization_07                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #07
$eDP_T3_Optimization_08                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #08
$eDP_T3_Optimization_09                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #09
$eDP_T3_Optimization_10                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #10
$eDP_T3_Optimization_11                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #11
$eDP_T3_Optimization_12                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #12
$eDP_T3_Optimization_13                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #13
$eDP_T3_Optimization_14                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #14
$eDP_T3_Optimization_15                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #15
$eDP_T3_Optimization_16                   1 bit       ; eDP T3 Optimization enable disabled VBT bit panel #16

$eDP_VSwingPreEmph_01                     4 bits      ; eDp selects VSwing Preemph table for panel #01
$eDP_VSwingPreEmph_02                     4 bits      ; eDp selects VSwing Preemph table for panel #02
$eDP_VSwingPreEmph_03                     4 bits      ; eDp selects VSwing Preemph table for panel #03
$eDP_VSwingPreEmph_04                     4 bits      ; eDp selects VSwing Preemph table for panel #04
$eDP_VSwingPreEmph_05                     4 bits      ; eDp selects VSwing Preemph table for panel #05
$eDP_VSwingPreEmph_06                     4 bits      ; eDp selects VSwing Preemph table for panel #06
$eDP_VSwingPreEmph_07                     4 bits      ; eDp selects VSwing Preemph table for panel #07
$eDP_VSwingPreEmph_08                     4 bits      ; eDp selects VSwing Preemph table for panel #08
$eDP_VSwingPreEmph_09                     4 bits      ; eDp selects VSwing Preemph table for panel #09
$eDP_VSwingPreEmph_10                     4 bits      ; eDp selects VSwing Preemph table for panel #10
$eDP_VSwingPreEmph_11                     4 bits      ; eDp selects VSwing Preemph table for panel #11
$eDP_VSwingPreEmph_12                     4 bits      ; eDp selects VSwing Preemph table for panel #12
$eDP_VSwingPreEmph_13                     4 bits      ; eDp selects VSwing Preemph table for panel #13
$eDP_VSwingPreEmph_14                     4 bits      ; eDp selects VSwing Preemph table for panel #14
$eDP_VSwingPreEmph_15                     4 bits      ; eDp selects VSwing Preemph table for panel #15
$eDP_VSwingPreEmph_16                     4 bits      ; eDp selects VSwing Preemph table for panel #16

$eDP_Fast_Link_Training_Supported_01      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #01
$eDP_Fast_Link_Training_Supported_02      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #02
$eDP_Fast_Link_Training_Supported_03      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #03
$eDP_Fast_Link_Training_Supported_04      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #04
$eDP_Fast_Link_Training_Supported_05      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #05
$eDP_Fast_Link_Training_Supported_06      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #06
$eDP_Fast_Link_Training_Supported_07      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #07
$eDP_Fast_Link_Training_Supported_08      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #08
$eDP_Fast_Link_Training_Supported_09      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #09
$eDP_Fast_Link_Training_Supported_10      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #10
$eDP_Fast_Link_Training_Supported_11      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #11
$eDP_Fast_Link_Training_Supported_12      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #12
$eDP_Fast_Link_Training_Supported_13      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #13
$eDP_Fast_Link_Training_Supported_14      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #14
$eDP_Fast_Link_Training_Supported_15      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #15
$eDP_Fast_Link_Training_Supported_16      1 bit       ; eDP Fast Link Training enable disable VBT bit panel #16

SKIP                                      2 bytes     ; Skip Enable Power State at DPCD 600h

$eDP_PwmOn_To_Bklt_Enable_Delay_01        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #01
$eDP_Bklt_Disable_To_PwmOff_Delay_01      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #01

$eDP_PwmOn_To_Bklt_Enable_Delay_02        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #02
$eDP_Bklt_Disable_To_PwmOff_Delay_02      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #02

$eDP_PwmOn_To_Bklt_Enable_Delay_03        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #03
$eDP_Bklt_Disable_To_PwmOff_Delay_03      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #03

$eDP_PwmOn_To_Bklt_Enable_Delay_04        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #04
$eDP_Bklt_Disable_To_PwmOff_Delay_04      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #04

$eDP_PwmOn_To_Bklt_Enable_Delay_05        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #05
$eDP_Bklt_Disable_To_PwmOff_Delay_05      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #05

$eDP_PwmOn_To_Bklt_Enable_Delay_06        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #06
$eDP_Bklt_Disable_To_PwmOff_Delay_06      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #06

$eDP_PwmOn_To_Bklt_Enable_Delay_07        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #07
$eDP_Bklt_Disable_To_PwmOff_Delay_07      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #07

$eDP_PwmOn_To_Bklt_Enable_Delay_08        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #08
$eDP_Bklt_Disable_To_PwmOff_Delay_08      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #08

$eDP_PwmOn_To_Bklt_Enable_Delay_09        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #09
$eDP_Bklt_Disable_To_PwmOff_Delay_09      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #09

$eDP_PwmOn_To_Bklt_Enable_Delay_10        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #10
$eDP_Bklt_Disable_To_PwmOff_Delay_10      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #10

$eDP_PwmOn_To_Bklt_Enable_Delay_11        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #11
$eDP_Bklt_Disable_To_PwmOff_Delay_11      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #11

$eDP_PwmOn_To_Bklt_Enable_Delay_12        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #12
$eDP_Bklt_Disable_To_PwmOff_Delay_12      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #12

$eDP_PwmOn_To_Bklt_Enable_Delay_13        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #13
$eDP_Bklt_Disable_To_PwmOff_Delay_13      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #13

$eDP_PwmOn_To_Bklt_Enable_Delay_14        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #14
$eDP_Bklt_Disable_To_PwmOff_Delay_14      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #14

$eDP_PwmOn_To_Bklt_Enable_Delay_15        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #15
$eDP_Bklt_Disable_To_PwmOff_Delay_15      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #15

$eDP_PwmOn_To_Bklt_Enable_Delay_16        2 bytes     ; Delay from Pwm On to Backlight Enable for Panel #16
$eDP_Bklt_Disable_To_PwmOff_Delay_16      2 bytes     ; Delay from Backlight Disable to Pwm Off for Panel #16

$eDP_Full_Link_Training_Params_Enable_01  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #01
$eDP_Full_Link_Training_Params_Enable_02  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #02
$eDP_Full_Link_Training_Params_Enable_03  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #03
$eDP_Full_Link_Training_Params_Enable_04  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #04
$eDP_Full_Link_Training_Params_Enable_05  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #05
$eDP_Full_Link_Training_Params_Enable_06  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #06
$eDP_Full_Link_Training_Params_Enable_07  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #07
$eDP_Full_Link_Training_Params_Enable_08  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #08
$eDP_Full_Link_Training_Params_Enable_09  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #09
$eDP_Full_Link_Training_Params_Enable_10  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #10
$eDP_Full_Link_Training_Params_Enable_11  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #11
$eDP_Full_Link_Training_Params_Enable_12  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #12
$eDP_Full_Link_Training_Params_Enable_13  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #13
$eDP_Full_Link_Training_Params_Enable_14  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #14
$eDP_Full_Link_Training_Params_Enable_15  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #15
$eDP_Full_Link_Training_Params_Enable_16  1 bit       ; eDP Full Link Training initial parameters in VBT enable bit panel #16

$eDP_Full_Link_Train_PreEmp_01            4 bits      ; Panel #01 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_01            4 bits      ; Panel #01 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_02            4 bits      ; Panel #02 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_02            4 bits      ; Panel #02 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_03            4 bits      ; Panel #03 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_03            4 bits      ; Panel #03 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_04            4 bits      ; Panel #04 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_04            4 bits      ; Panel #04 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_05            4 bits      ; Panel #05 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_05            4 bits      ; Panel #05 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_06            4 bits      ; Panel #06 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_06            4 bits      ; Panel #06 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_07            4 bits      ; Panel #07 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_07            4 bits      ; Panel #07 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_08            4 bits      ; Panel #08 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_08            4 bits      ; Panel #08 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_09            4 bits      ; Panel #09 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_09            4 bits      ; Panel #09 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_10            4 bits      ; Panel #10 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_10            4 bits      ; Panel #10 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_11            4 bits      ; Panel #11 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_11            4 bits      ; Panel #11 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_12            4 bits      ; Panel #12 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_12            4 bits      ; Panel #12 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_13            4 bits      ; Panel #13 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_13            4 bits      ; Panel #13 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_14            4 bits      ; Panel #14 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_14            4 bits      ; Panel #14 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_15            4 bits      ; Panel #15 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_15            4 bits      ; Panel #15 Full link training initial Voltage Swing

$eDP_Full_Link_Train_PreEmp_16            4 bits      ; Panel #16 Full link training initial Pre-emphasis
$eDP_Full_Link_Train_Vswing_16            4 bits      ; Panel #16 Full link training initial Voltage Swing

$eDP_Apical_Display_Ip_Enable_01          1 bit       ; Panel #01 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_02          1 bit       ; Panel #02 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_03          1 bit       ; Panel #03 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_04          1 bit       ; Panel #04 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_05          1 bit       ; Panel #05 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_06          1 bit       ; Panel #06 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_07          1 bit       ; Panel #07 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_08          1 bit       ; Panel #08 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_09          1 bit       ; Panel #09 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_10          1 bit       ; Panel #10 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_11          1 bit       ; Panel #11 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_12          1 bit       ; Panel #12 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_13          1 bit       ; Panel #13 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_14          1 bit       ; Panel #14 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_15          1 bit       ; Panel #15 Apical Display IP Enable bit
$eDP_Apical_Display_Ip_Enable_16          1 bit       ; Panel #16 Apical Display IP Enable bit

; Panel #01 Apical Display IP parameters
$eDP_Panel_Oui_01                         4 bytes     ; Panel #01 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_01                 4 bytes     ; Panel #01 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_01             4 bytes     ; Panel #01 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_01                4 bytes     ; Panel #01 Apical specific DPCD option select
$eDP_Dpcd_Backlight_01                    4 bytes     ; Panel #01 Apical specific DPCD backlight
$eDP_Ambient_Light_01                     4 bytes     ; Panel #01 Apical specific Ambient light
$eDP_Backlight_Scale_01                   4 bytes     ; Panel #01 Apical specific backlight scale value

; Panel #02 Apical Display IP parameters
$eDP_Panel_Oui_02                         4 bytes     ; Panel #02 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_02                 4 bytes     ; Panel #02 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_02             4 bytes     ; Panel #02 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_02                4 bytes     ; Panel #02 Apical specific DPCD option select
$eDP_Dpcd_Backlight_02                    4 bytes     ; Panel #02 Apical specific DPCD backlight
$eDP_Ambient_Light_02                     4 bytes     ; Panel #02 Apical specific Ambient light
$eDP_Backlight_Scale_02                   4 bytes     ; Panel #02 Apical specific backlight scale value

; Panel #03 Apical Display IP parameters
$eDP_Panel_Oui_03                         4 bytes     ; Panel #03 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_03                 4 bytes     ; Panel #03 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_03             4 bytes     ; Panel #03 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_03                4 bytes     ; Panel #03 Apical specific DPCD option select
$eDP_Dpcd_Backlight_03                    4 bytes     ; Panel #03 Apical specific DPCD backlight
$eDP_Ambient_Light_03                     4 bytes     ; Panel #03 Apical specific Ambient light
$eDP_Backlight_Scale_03                   4 bytes     ; Panel #03 Apical specific backlight scale value

; Panel #04 Apical Display IP parameters
$eDP_Panel_Oui_04                         4 bytes     ; Panel #04 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_04                 4 bytes     ; Panel #04 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_04             4 bytes     ; Panel #04 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_04                4 bytes     ; Panel #04 Apical specific DPCD option select
$eDP_Dpcd_Backlight_04                    4 bytes     ; Panel #04 Apical specific DPCD backlight
$eDP_Ambient_Light_04                     4 bytes     ; Panel #04 Apical specific Ambient light
$eDP_Backlight_Scale_04                   4 bytes     ; Panel #04 Apical specific backlight scale value

; Panel #05 Apical Display IP parameters
$eDP_Panel_Oui_05                         4 bytes     ; Panel #05 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_05                 4 bytes     ; Panel #05 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_05             4 bytes     ; Panel #05 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_05                4 bytes     ; Panel #05 Apical specific DPCD option select
$eDP_Dpcd_Backlight_05                    4 bytes     ; Panel #05 Apical specific DPCD backlight
$eDP_Ambient_Light_05                     4 bytes     ; Panel #05 Apical specific Ambient light
$eDP_Backlight_Scale_05                   4 bytes     ; Panel #05 Apical specific backlight scale value

; Panel #06 Apical Display IP parameters
$eDP_Panel_Oui_06                         4 bytes     ; Panel #06 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_06                 4 bytes     ; Panel #06 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_06             4 bytes     ; Panel #06 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_06                4 bytes     ; Panel #06 Apical specific DPCD option select
$eDP_Dpcd_Backlight_06                    4 bytes     ; Panel #06 Apical specific DPCD backlight
$eDP_Ambient_Light_06                     4 bytes     ; Panel #06 Apical specific Ambient light
$eDP_Backlight_Scale_06                   4 bytes     ; Panel #06 Apical specific backlight scale value

; Panel #07 Apical Display IP parameters
$eDP_Panel_Oui_07                         4 bytes     ; Panel #07 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_07                 4 bytes     ; Panel #07 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_07             4 bytes     ; Panel #07 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_07                4 bytes     ; Panel #07 Apical specific DPCD option select
$eDP_Dpcd_Backlight_07                    4 bytes     ; Panel #07 Apical specific DPCD backlight
$eDP_Ambient_Light_07                     4 bytes     ; Panel #07 Apical specific Ambient light
$eDP_Backlight_Scale_07                   4 bytes     ; Panel #07 Apical specific backlight scale value

; Panel #08 Apical Display IP parameters
$eDP_Panel_Oui_08                         4 bytes     ; Panel #08 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_08                 4 bytes     ; Panel #08 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_08             4 bytes     ; Panel #08 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_08                4 bytes     ; Panel #08 Apical specific DPCD option select
$eDP_Dpcd_Backlight_08                    4 bytes     ; Panel #08 Apical specific DPCD backlight
$eDP_Ambient_Light_08                     4 bytes     ; Panel #08 Apical specific Ambient light
$eDP_Backlight_Scale_08                   4 bytes     ; Panel #08 Apical specific backlight scale value

; Panel #09 Apical Display IP parameters
$eDP_Panel_Oui_09                         4 bytes     ; Panel #09 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_09                 4 bytes     ; Panel #09 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_09             4 bytes     ; Panel #09 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_09                4 bytes     ; Panel #09 Apical specific DPCD option select
$eDP_Dpcd_Backlight_09                    4 bytes     ; Panel #09 Apical specific DPCD backlight
$eDP_Ambient_Light_09                     4 bytes     ; Panel #09 Apical specific Ambient light
$eDP_Backlight_Scale_09                   4 bytes     ; Panel #09 Apical specific backlight scale value

; Panel #10 Apical Display IP parameters
$eDP_Panel_Oui_10                         4 bytes     ; Panel #10 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_10                 4 bytes     ; Panel #10 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_10             4 bytes     ; Panel #10 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_10                4 bytes     ; Panel #10 Apical specific DPCD option select
$eDP_Dpcd_Backlight_10                    4 bytes     ; Panel #10 Apical specific DPCD backlight
$eDP_Ambient_Light_10                     4 bytes     ; Panel #10 Apical specific Ambient light
$eDP_Backlight_Scale_10                   4 bytes     ; Panel #10 Apical specific backlight scale value

; Panel #11 Apical Display IP parameters
$eDP_Panel_Oui_11                         4 bytes     ; Panel #11 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_11                 4 bytes     ; Panel #11 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_11             4 bytes     ; Panel #11 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_11                4 bytes     ; Panel #11 Apical specific DPCD option select
$eDP_Dpcd_Backlight_11                    4 bytes     ; Panel #11 Apical specific DPCD backlight
$eDP_Ambient_Light_11                     4 bytes     ; Panel #11 Apical specific Ambient light
$eDP_Backlight_Scale_11                   4 bytes     ; Panel #11 Apical specific backlight scale value

; Panel #12 Apical Display IP parameters
$eDP_Panel_Oui_12                         4 bytes     ; Panel #12 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_12                 4 bytes     ; Panel #12 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_12             4 bytes     ; Panel #12 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_12                4 bytes     ; Panel #12 Apical specific DPCD option select
$eDP_Dpcd_Backlight_12                    4 bytes     ; Panel #12 Apical specific DPCD backlight
$eDP_Ambient_Light_12                     4 bytes     ; Panel #12 Apical specific Ambient light
$eDP_Backlight_Scale_12                   4 bytes     ; Panel #12 Apical specific backlight scale value

; Panel #13 Apical Display IP parameters
$eDP_Panel_Oui_13                         4 bytes     ; Panel #13 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_13                 4 bytes     ; Panel #13 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_13             4 bytes     ; Panel #13 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_13                4 bytes     ; Panel #13 Apical specific DPCD option select
$eDP_Dpcd_Backlight_13                    4 bytes     ; Panel #13 Apical specific DPCD backlight
$eDP_Ambient_Light_13                     4 bytes     ; Panel #13 Apical specific Ambient light
$eDP_Backlight_Scale_13                   4 bytes     ; Panel #13 Apical specific backlight scale value

; Panel #14 Apical Display IP parameters
$eDP_Panel_Oui_14                         4 bytes     ; Panel #14 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_14                 4 bytes     ; Panel #14 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_14             4 bytes     ; Panel #14 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_14                4 bytes     ; Panel #14 Apical specific DPCD option select
$eDP_Dpcd_Backlight_14                    4 bytes     ; Panel #14 Apical specific DPCD backlight
$eDP_Ambient_Light_14                     4 bytes     ; Panel #14 Apical specific Ambient light
$eDP_Backlight_Scale_14                   4 bytes     ; Panel #14 Apical specific backlight scale value

; Panel #15 Apical Display IP parameters
$eDP_Panel_Oui_15                         4 bytes     ; Panel #15 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_15                 4 bytes     ; Panel #15 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_15             4 bytes     ; Panel #15 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_15                4 bytes     ; Panel #15 Apical specific DPCD option select
$eDP_Dpcd_Backlight_15                    4 bytes     ; Panel #15 Apical specific DPCD backlight
$eDP_Ambient_Light_15                     4 bytes     ; Panel #15 Apical specific Ambient light
$eDP_Backlight_Scale_15                   4 bytes     ; Panel #15 Apical specific backlight scale value

; Panel #16 Apical Display IP parameters
$eDP_Panel_Oui_16                         4 bytes     ; Panel #16 Apical specific Panel OUI
$eDP_Dpcd_Base_Address_16                 4 bytes     ; Panel #16 Apical specific DPCD base address
$eDP_Dpcd_Irdidix_Control0_16             4 bytes     ; Panel #16 Apical specific DPCD Idridix control 0
$eDP_Dpcd_Option_Select_16                4 bytes     ; Panel #16 Apical specific DPCD option select
$eDP_Dpcd_Backlight_16                    4 bytes     ; Panel #16 Apical specific DPCD backlight
$eDP_Ambient_Light_16                     4 bytes     ; Panel #16 Apical specific Ambient light
$eDP_Backlight_Scale_16                   4 bytes     ; Panel #16 Apical specific backlight scale value

;==============================================================================
; Block 28 - EDID-less EFP support - Panel data
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size
$EFP1_DTD                                 18 bytes    ; DTD for Device 1 DP/HDMI/DVI panel
$EFP2_DTD                                 18 bytes    ; DTD for Device 2 DP/HDMI/DVI panel
$EFP3_DTD                                 18 bytes    ; DTD for Device 3 DP/HDMI/DVI panel
$EFP4_DTD                                 18 bytes    ; DTD for Device 4 DP/HDMI/DVI panel

;==============================================================================
; Block 31 - VBIOS/Driver Toggle list for SKL/KBL
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size
SKIP                                      92 bytes    ; Skip Toggle lists
ALIGN

;==============================================================================
; Block 32 - Display Removal Configurations for SKL/KBL
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size
SKIP                                      2 bytes     ; Table Row/Size Data
SKIP                                      30 bytes    ; Skip Removed displays table

;==============================================================================
; Block 40 - Start of LVDS BMP Structure Definition
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size

$bmp_Panel_type                           1 byte      ; Flat panel type
SKIP                                      1 byte      ; Obsoleted
SKIP                                      6 bits      ; Skip bits 0:5 of bmp_LVDS_Capabilities
$bmp_Panel_EDID                           1 bit       ; LVDS panel EDID enable/disable bit
SKIP                                      1 bit       ; Skip bit 7 of bmp_LVDS_Capabilities
SKIP                                      1 byte      ; Skip bits 8:15 of bmp_LVDS_Capabilities

; INT_LVDS_Panel_Channel_Bits
SKIP                                      4 bytes     ; Obsolete: Was used for LVDS panel channel type.

; LVDS Spread Spectrum Clock
; Enable/Disable SSC
$Enable_SSC01                             1 bit       ; Panel #01, 0=No, 1=Yes
$Enable_SSC02                             1 bit       ; Panel #02, 0=No, 1=Yes
$Enable_SSC03                             1 bit       ; Panel #03, 0=No, 1=Yes
$Enable_SSC04                             1 bit       ; Panel #04, 0=No, 1=Yes
$Enable_SSC05                             1 bit       ; Panel #05, 0=No, 1=Yes
$Enable_SSC06                             1 bit       ; Panel #06, 0=No, 1=Yes
$Enable_SSC07                             1 bit       ; Panel #07, 0=No, 1=Yes
$Enable_SSC08                             1 bit       ; Panel #08, 0=No, 1=Yes
$Enable_SSC09                             1 bit       ; Panel #09, 0=No, 1=Yes
$Enable_SSC10                             1 bit       ; Panel #10, 0=No 1=Yes
$Enable_SSC11                             1 bit       ; Panel #11, 0=No, 1=Yes
$Enable_SSC12                             1 bit       ; Panel #12, 0=No, 1=Yes
$Enable_SSC13                             1 bit       ; Panel #13, 0=No, 1=Yes
$Enable_SSC14                             1 bit       ; Panel #14, 0=No, 1=Yes
$Enable_SSC15                             1 bit       ; Panel #15, 0=No, 1=Yes
$Enable_SSC16                             1 bit       ; Panel #16, 0=No, 1=Yes

SKIP                                      2 bytes     ; Obsolete: Was used for SSC frequency for LVDS.

SKIP                                      2 bytes     ; Obsolete: Was used for Disable SSC in DDT mode.

SKIP                                      2 bytes     ; Obsolete: Was used for panel color depth for LVDS panels.

$DPS_Panel_Type_01                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_02                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_03                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_04                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_05                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_06                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_07                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_08                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_09                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_10                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_11                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_12                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_13                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_14                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_15                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_16                        2 bits      ; 00 = Static DRRS, 01 = Redundant, 10 = Seamless

$Blt_Control_01                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_02                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_03                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_04                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_05                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_06                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_07                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_08                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_09                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_10                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_11                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_12                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_13                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_14                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_15                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_16                           2 bits      ; 00 = Default, 01 = CCFL backlight, 10 = LED backlight

$LcdVcc_On_During_S0_State_01             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #01
$LcdVcc_On_During_S0_State_02             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #02
$LcdVcc_On_During_S0_State_03             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #03
$LcdVcc_On_During_S0_State_04             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #04
$LcdVcc_On_During_S0_State_05             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #05
$LcdVcc_On_During_S0_State_06             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #06
$LcdVcc_On_During_S0_State_07             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #07
$LcdVcc_On_During_S0_State_08             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #08
$LcdVcc_On_During_S0_State_09             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #09
$LcdVcc_On_During_S0_State_10             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #10
$LcdVcc_On_During_S0_State_11             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #11
$LcdVcc_On_During_S0_State_12             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #12
$LcdVcc_On_During_S0_State_13             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #13
$LcdVcc_On_During_S0_State_14             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #14
$LcdVcc_On_During_S0_State_15             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #15
$LcdVcc_On_During_S0_State_16             1 bit       ; Enable flag to keep LCDVCC on during S0 state bit for panel #16

;==============================================================================
; Block 41 - Flat Panel Data Tables Pointers
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; SKIP block ID and size
SKIP                                      1 byte      ; Skip entries number byte

$LVDS_Tbl_Ptr_01                          2 bytes
$LVDS_Tbl_Size_01                         1 byte
$LVDS_Tbl_01, $LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes
$DVO_Tbl_Ptr_01                           2 bytes
$DVO_Tbl_Size_01                          1 byte
$DVO_Tbl_01, $DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte
$LVDS_PnP_ID_Ptr_01                       2 bytes
$LVDS_PnP_ID_Size_01                      1 byte
$LVDS_PnP_ID_01, $LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte

$LVDS_Tbl_Ptr_02                          2 bytes
$LVDS_Tbl_Size_02                         1 byte
$LVDS_Tbl_02, $LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes
$DVO_Tbl_Ptr_02                           2 bytes
$DVO_Tbl_Size_02                          1 byte
$DVO_Tbl_02, $DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte
$LVDS_PnP_ID_Ptr_02                       2 bytes
$LVDS_PnP_ID_Size_02                      1 byte
$LVDS_PnP_ID_02, $LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte

$LVDS_Tbl_Ptr_03                          2 bytes
$LVDS_Tbl_Size_03                         1 byte
$LVDS_Tbl_03, $LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes
$DVO_Tbl_Ptr_03                           2 bytes
$DVO_Tbl_Size_03                          1 byte
$DVO_Tbl_03, $DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte
$LVDS_PnP_ID_Ptr_03                       2 bytes
$LVDS_PnP_ID_Size_03                      1 byte
$LVDS_PnP_ID_03, $LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte

$LVDS_Tbl_Ptr_04                          2 bytes
$LVDS_Tbl_Size_04                         1 byte
$LVDS_Tbl_04, $LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes
$DVO_Tbl_Ptr_04                           2 bytes
$DVO_Tbl_Size_04                          1 byte
$DVO_Tbl_04, $DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte
$LVDS_PnP_ID_Ptr_04                       2 bytes
$LVDS_PnP_ID_Size_04                      1 byte
$LVDS_PnP_ID_04, $LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte

$LVDS_Tbl_Ptr_05                          2 bytes
$LVDS_Tbl_Size_05                         1 byte
$LVDS_Tbl_05, $LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes
$DVO_Tbl_Ptr_05                           2 bytes
$DVO_Tbl_Size_05                          1 byte
$DVO_Tbl_05, $DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte
$LVDS_PnP_ID_Ptr_05                       2 bytes
$LVDS_PnP_ID_Size_05                      1 byte
$LVDS_PnP_ID_05, $LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte

$LVDS_Tbl_Ptr_06                          2 bytes
$LVDS_Tbl_Size_06                         1 byte
$LVDS_Tbl_06, $LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes
$DVO_Tbl_Ptr_06                           2 bytes
$DVO_Tbl_Size_06                          1 byte
$DVO_Tbl_06, $DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte
$LVDS_PnP_ID_Ptr_06                       2 bytes
$LVDS_PnP_ID_Size_06                      1 byte
$LVDS_PnP_ID_06, $LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte

$LVDS_Tbl_Ptr_07                          2 bytes
$LVDS_Tbl_Size_07                         1 byte
$LVDS_Tbl_07, $LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes
$DVO_Tbl_Ptr_07                           2 bytes
$DVO_Tbl_Size_07                          1 byte
$DVO_Tbl_07, $DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte
$LVDS_PnP_ID_Ptr_07                       2 bytes
$LVDS_PnP_ID_Size_07                      1 byte
$LVDS_PnP_ID_07, $LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte

$LVDS_Tbl_Ptr_08                          2 bytes
$LVDS_Tbl_Size_08                         1 byte
$LVDS_Tbl_08, $LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes
$DVO_Tbl_Ptr_08                           2 bytes
$DVO_Tbl_Size_08                          1 byte
$DVO_Tbl_08, $DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte
$LVDS_PnP_ID_Ptr_08                       2 bytes
$LVDS_PnP_ID_Size_08                      1 byte
$LVDS_PnP_ID_08, $LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte

$LVDS_Tbl_Ptr_09                          2 bytes
$LVDS_Tbl_Size_09                         1 byte
$LVDS_Tbl_09, $LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes
$DVO_Tbl_Ptr_09                           2 bytes
$DVO_Tbl_Size_09                          1 byte
$DVO_Tbl_09, $DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte
$LVDS_PnP_ID_Ptr_09                       2 bytes
$LVDS_PnP_ID_Size_09                      1 byte
$LVDS_PnP_ID_09, $LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte

$LVDS_Tbl_Ptr_10                          2 bytes
$LVDS_Tbl_Size_10                         1 byte
$LVDS_Tbl_10, $LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes
$DVO_Tbl_Ptr_10                           2 bytes
$DVO_Tbl_Size_10                          1 byte
$DVO_Tbl_10, $DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte
$LVDS_PnP_ID_Ptr_10                       2 bytes
$LVDS_PnP_ID_Size_10                      1 byte
$LVDS_PnP_ID_10, $LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte

$LVDS_Tbl_Ptr_11                          2 bytes
$LVDS_Tbl_Size_11                         1 byte
$LVDS_Tbl_11, $LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes
$DVO_Tbl_Ptr_11                           2 bytes
$DVO_Tbl_Size_11                          1 byte
$DVO_Tbl_11, $DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte
$LVDS_PnP_ID_Ptr_11                       2 bytes
$LVDS_PnP_ID_Size_11                      1 byte
$LVDS_PnP_ID_11, $LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte

$LVDS_Tbl_Ptr_12                          2 bytes
$LVDS_Tbl_Size_12                         1 byte
$LVDS_Tbl_12, $LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes
$DVO_Tbl_Ptr_12                           2 bytes
$DVO_Tbl_Size_12                          1 byte
$DVO_Tbl_12, $DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte
$LVDS_PnP_ID_Ptr_12                       2 bytes
$LVDS_PnP_ID_Size_12                      1 byte
$LVDS_PnP_ID_12, $LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte

$LVDS_Tbl_Ptr_13                          2 bytes
$LVDS_Tbl_Size_13                         1 byte
$LVDS_Tbl_13, $LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes
$DVO_Tbl_Ptr_13                           2 bytes
$DVO_Tbl_Size_13                          1 byte
$DVO_Tbl_13, $DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte
$LVDS_PnP_ID_Ptr_13                       2 bytes
$LVDS_PnP_ID_Size_13                      1 byte
$LVDS_PnP_ID_13, $LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte

$LVDS_Tbl_Ptr_14                          2 bytes
$LVDS_Tbl_Size_14                         1 byte
$LVDS_Tbl_14, $LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes
$DVO_Tbl_Ptr_14                           2 bytes
$DVO_Tbl_Size_14                          1 byte
$DVO_Tbl_14, $DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte
$LVDS_PnP_ID_Ptr_14                       2 bytes
$LVDS_PnP_ID_Size_14                      1 byte
$LVDS_PnP_ID_14, $LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte

$LVDS_Tbl_Ptr_15                          2 bytes
$LVDS_Tbl_Size_15                         1 byte
$LVDS_Tbl_15, $LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes
$DVO_Tbl_Ptr_15                           2 bytes
$DVO_Tbl_Size_15                          1 byte
$DVO_Tbl_15, $DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte
$LVDS_PnP_ID_Ptr_15                       2 bytes
$LVDS_PnP_ID_Size_15                      1 byte
$LVDS_PnP_ID_15, $LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte

$LVDS_Tbl_Ptr_16                          2 bytes
$LVDS_Tbl_Size_16                         1 byte
$LVDS_Tbl_16, $LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes
$DVO_Tbl_Ptr_16                           2 bytes
$DVO_Tbl_Size_16                          1 byte
$DVO_Tbl_16, $DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte
$LVDS_PnP_ID_Ptr_16                       2 bytes
$LVDS_PnP_ID_Size_16                      1 byte
$LVDS_PnP_ID_16, $LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte

$LVDS_Name_Ptr                            2 bytes
$LVDS_Name_Sz                             1 byte      ; Skip LFP_PanelName offset and panel name length

;==============================================================================
; Block 42 - Flat Panel Data Tables
;------------------------------------------------------------------------------
SKIP                                      3 bytes     ; Skip block ID and size

; Flat Panel #01
$Panel_Width_01                           2 bytes     ; Panel Width
$Panel_Height_01                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #02
$Panel_Width_02                           2 bytes     ; Panel Width
$Panel_Height_02                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #03
$Panel_Width_03                           2 bytes     ; Panel Width
$Panel_Height_03                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #04
$Panel_Width_04                           2 bytes     ; Panel Width
$Panel_Height_04                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #05
$Panel_Width_05                           2 bytes     ; Panel Width
$Panel_Height_05                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #06
$Panel_Width_06                           2 bytes     ; Panel Width
$Panel_Height_06                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #07

$Panel_Width_07                           2 bytes     ; Panel Width
$Panel_Height_07                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #08

$Panel_Width_08                           2 bytes     ; Panel Width
$Panel_Height_08                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #09
$Panel_Width_09                           2 bytes     ; Panel Width
$Panel_Height_09                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #10
$Panel_Width_10                           2 bytes     ; Panel Width
$Panel_Height_10                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #11
$Panel_Width_11                           2 bytes     ; Panel Width
$Panel_Height_11                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #12
$Panel_Width_12                           2 bytes     ; Panel Width
$Panel_Height_12                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #13
$Panel_Width_13                           2 bytes     ; Panel Width
$Panel_Height_13                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #14
$Panel_Width_14                           2 bytes     ; Panel Width
$Panel_Height_14                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #15
$Panel_Width_15                           2 bytes     ; Panel Width
$Panel_Height_15                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

; Flat Panel #16
$Panel_Width_16                           2 bytes     ; Panel Width
$Panel_Height_16                          2 bytes     ; Panel Height

SKIP                                      34 bytes    ; Skip remaining size of FP Data structure.
SKIP                                      18 bytes    ; DTD
SKIP                                      10 bytes    ; PnP ID

$Panel_Name_01                            13 bytes    ; LFP Panel Name
$Panel_Name_02                            13 bytes    ; LFP Panel Name
$Panel_Name_03                            13 bytes    ; LFP Panel Name
$Panel_Name_04                            13 bytes    ; LFP Panel Name
$Panel_Name_05                            13 bytes    ; LFP Panel Name
$Panel_Name_06                            13 bytes    ; LFP Panel Name
$Panel_Name_07                            13 bytes    ; LFP Panel Name
$Panel_Name_08                            13 bytes    ; LFP Panel Name
$Panel_Name_09                            13 bytes    ; LFP Panel Name
$Panel_Name_10                            13 bytes    ; LFP Panel Name
$Panel_Name_11                            13 bytes    ; LFP Panel Name
$Panel_Name_12                            13 bytes    ; LFP Panel Name
$Panel_Name_13                            13 bytes    ; LFP Panel Name
$Panel_Name_14                            13 bytes    ; LFP Panel Name
$Panel_Name_15                            13 bytes    ; LFP Panel Name
$Panel_Name_16                            13 bytes    ; LFP Panel Name

SKIP                                      2 bytes     ; EnableScaling

SKIP                                      16 bytes    ; Seamless_DRRS_Min_RR

;==============================================================================
; Block 43 - BLC (Backlight Control) Support
;------------------------------------------------------------------------------

SKIP                                      3 bytes     ; Skip block ID and size
SKIP                                      1 byte      ; Skip row size

; Flat Panel #01
$BLC_Inv_Type_01                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_01                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_01                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_01                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_01                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_01                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_01                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_01                    1 byte      ; I2C inverter command code

; Flat Panel #02
$BLC_Inv_Type_02                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_02                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_02                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_02                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_02                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_02                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_02                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_02                    1 byte      ; I2C inverter command code

; Flat Panel #03
$BLC_Inv_Type_03                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_03                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_03                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_03                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_03                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_03                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_03                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_03                    1 byte      ; I2C inverter command code

; Flat Panel #04
$BLC_Inv_Type_04                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_04                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_04                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_04                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_04                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_04                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_04                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_04                    1 byte      ; I2C inverter command code

; Flat Panel #05
$BLC_Inv_Type_05                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_05                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_05                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_05                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_05                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_05                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_05                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_05                    1 byte      ; I2C inverter command code

; Flat Panel #06
$BLC_Inv_Type_06                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_06                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_06                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_06                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_06                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_06                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_06                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_06                    1 byte      ; I2C inverter command code

; Flat Panel #07
$BLC_Inv_Type_07                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_07                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_07                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_07                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_07                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_07                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_07                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_07                    1 byte      ; I2C inverter command code

; Flat Panel #08
$BLC_Inv_Type_08                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_08                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_08                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_08                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_08                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_08                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_08                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_08                    1 byte      ; I2C inverter command code

; Flat Panel #09
$BLC_Inv_Type_09                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_09                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_09                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_09                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_09                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_09                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_09                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_09                    1 byte      ; I2C inverter command code

; Flat Panel #10
$BLC_Inv_Type_10                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_10                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_10                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_10                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_10                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_10                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_10                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_10                    1 byte      ; I2C inverter command code

; Flat Panel #11
$BLC_Inv_Type_11                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_11                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_11                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_11                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_11                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_11                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_11                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_11                    1 byte      ; I2C inverter command code

; Flat Panel #12
$BLC_Inv_Type_12                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_12                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_12                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_12                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_12                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_12                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_12                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_12                    1 byte      ; I2C inverter command code

; Flat Panel #13
$BLC_Inv_Type_13                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_13                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_13                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_13                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_13                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_13                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_13                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_13                    1 byte      ; I2C inverter command code

; Flat Panel #14
$BLC_Inv_Type_14                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_14                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_14                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_14                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_14                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_14                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_14                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_14                    1 byte      ; I2C inverter command code

; Flat Panel #15
$BLC_Inv_Type_15                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_15                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_15                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_15                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_15                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_15                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_15                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_15                    1 byte      ; I2C inverter command code

; Flat Panel #16
$BLC_Inv_Type_16                          2 bits      ; BLC inverter type
$BLC_Inv_Polarity_16                      1 bit       ; BLC inverter polarity
$BLC_GPIO_Pins_16                         3 bits      ; BLC inverter GPIO Pins
$BLC_GMBus_Speed_16                       2 bits      ; BLC inverter GMBus speed
$PWM_Frequency_16                         2 bytes     ; PWM inverter frequency
$BLC_Min_Brightness_16                    1 byte      ; Minimum Brightness, 0 - 255
$BLC_I2C_Addr_16                          1 byte      ; I2C inverter Slave address
$BLC_Brightness_Cmd_16                    1 byte      ; I2C inverter command code

$POST_BL_Brightness_01                    1 byte      ; Intial brightness value at POST for Flat Panel #01
$POST_BL_Brightness_02                    1 byte      ; Intial brightness value at POST for Flat Panel #02
$POST_BL_Brightness_03                    1 byte      ; Intial brightness value at POST for Flat Panel #03
$POST_BL_Brightness_04                    1 byte      ; Intial brightness value at POST for Flat Panel #04
$POST_BL_Brightness_05                    1 byte      ; Intial brightness value at POST for Flat Panel #05
$POST_BL_Brightness_06                    1 byte      ; Intial brightness value at POST for Flat Panel #06
$POST_BL_Brightness_07                    1 byte      ; Intial brightness value at POST for Flat Panel #07
$POST_BL_Brightness_08                    1 byte      ; Intial brightness value at POST for Flat Panel #08
$POST_BL_Brightness_09                    1 byte      ; Intial brightness value at POST for Flat Panel #09
$POST_BL_Brightness_10                    1 byte      ; Intial brightness value at POST for Flat Panel #10
$POST_BL_Brightness_11                    1 byte      ; Intial brightness value at POST for Flat Panel #11
$POST_BL_Brightness_12                    1 byte      ; Intial brightness value at POST for Flat Panel #12
$POST_BL_Brightness_13                    1 byte      ; Intial brightness value at POST for Flat Panel #13
$POST_BL_Brightness_14                    1 byte      ; Intial brightness value at POST for Flat Panel #14
$POST_BL_Brightness_15                    1 byte      ; Intial brightness value at POST for Flat Panel #15
$POST_BL_Brightness_16                    1 byte      ; Intial brightness value at POST for Flat Panel #16

$Lfp_Pwm_Source_Selection_01              4 bits      ; Pwm Source Selection for Panel #1
$Lfp_Pwm_Controller_Selection_01          4 bits      ; Pwm Controller Selection for Panel #1

$Lfp_Pwm_Source_Selection_02              4 bits      ; Pwm Source Selection for Panel #2
$Lfp_Pwm_Controller_Selection_02          4 bits      ; Pwm Controller Selection for Panel #2

$Lfp_Pwm_Source_Selection_03              4 bits      ; Pwm Source Selection for Panel #3
$Lfp_Pwm_Controller_Selection_03          4 bits      ; Pwm Controller Selection for Panel #3

$Lfp_Pwm_Source_Selection_04              4 bits      ; Pwm Source Selection for Panel #4
$Lfp_Pwm_Controller_Selection_04          4 bits      ; Pwm Controller Selection for Panel #4

$Lfp_Pwm_Source_Selection_05              4 bits      ; Pwm Source Selection for Panel #5
$Lfp_Pwm_Controller_Selection_05          4 bits      ; Pwm Controller Selection for Panel #5

$Lfp_Pwm_Source_Selection_06              4 bits      ; Pwm Source Selection for Panel #6
$Lfp_Pwm_Controller_Selection_06          4 bits      ; Pwm Controller Selection for Panel #6

$Lfp_Pwm_Source_Selection_07              4 bits      ; Pwm Source Selection for Panel #7
$Lfp_Pwm_Controller_Selection_07          4 bits      ; Pwm Controller Selection for Panel #7

$Lfp_Pwm_Source_Selection_08              4 bits      ; Pwm Source Selection for Panel #8
$Lfp_Pwm_Controller_Selection_08          4 bits      ; Pwm Controller Selection for Panel #8

$Lfp_Pwm_Source_Selection_09              4 bits      ; Pwm Source Selection for Panel #9
$Lfp_Pwm_Controller_Selection_09          4 bits      ; Pwm Controller Selection for Panel #9

$Lfp_Pwm_Source_Selection_10              4 bits      ; Pwm Source Selection for Panel #10
$Lfp_Pwm_Controller_Selection_10          4 bits      ; Pwm Controller Selection for Panel #10

$Lfp_Pwm_Source_Selection_11              4 bits      ; Pwm Source Selection for Panel #11
$Lfp_Pwm_Controller_Selection_11          4 bits      ; Pwm Controller Selection for Panel #11

$Lfp_Pwm_Source_Selection_12              4 bits      ; Pwm Source Selection for Panel #12
$Lfp_Pwm_Controller_Selection_12          4 bits      ; Pwm Controller Selection for Panel #12

$Lfp_Pwm_Source_Selection_13              4 bits      ; Pwm Source Selection for Panel #13
$Lfp_Pwm_Controller_Selection_13          4 bits      ; Pwm Controller Selection for Panel #13

$Lfp_Pwm_Source_Selection_14              4 bits      ; Pwm Source Selection for Panel #14
$Lfp_Pwm_Controller_Selection_14          4 bits      ; Pwm Controller Selection for Panel #14

$Lfp_Pwm_Source_Selection_15              4 bits      ; Pwm Source Selection for Panel #15
$Lfp_Pwm_Controller_Selection_15          4 bits      ; Pwm Controller Selection for Panel #15

$Lfp_Pwm_Source_Selection_16              4 bits      ; Pwm Source Selection for Panel #16
$Lfp_Pwm_Controller_Selection_16          4 bits      ; Pwm Controller Selection for Panel #16

;==============================================================================
; Block 44 - BIA (Backlight Image Adaption) Support
;------------------------------------------------------------------------------

SKIP                                      3 bytes     ; Skip block ID and size

SKIP                                      1 bit       ; Reserved
$BIA_Aggress_Level                        3 bits      ; Power Conservation Preference level
SKIP                                      3 bits      ; Reserved
SKIP                                      1 bit
ALIGN

$ALS_Response_Data                        20 bytes    ; ALS Response Data

;==============================================================================
; Block 46 - Chromaticity  Support
;------------------------------------------------------------------------------

SKIP                                      3 bytes     ; Skip block ID and size

; Flat Panel #01
$Chromacity_Enable_01                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_01                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_01                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_01                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_01                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_01                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_01                               1 byte      ; Green x coordinate at 1Dh
$Green_y_01                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_01                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_01                                1 byte      ; Blue y coordinate at 20h
$White_x_01                               1 byte      ; White x coordiante at 21h
$White_y_01                               1 byte      ; White y coordinate at 22h

; Flat Panel #02
$Chromacity_Enable_02                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_02                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_02                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_02                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_02                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_02                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_02                               1 byte      ; Green x coordinate at 1Dh
$Green_y_02                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_02                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_02                                1 byte      ; Blue y coordinate at 20h
$White_x_02                               1 byte      ; White x coordiante at 21h
$White_y_02                               1 byte      ; White y coordinate at 22h

; Flat Panel #03
$Chromacity_Enable_03                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_03                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_03                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_03                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_03                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_03                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_03                               1 byte      ; Green x coordinate at 1Dh
$Green_y_03                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_03                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_03                                1 byte      ; Blue y coordinate at 20h
$White_x_03                               1 byte      ; White x coordiante at 21h
$White_y_03                               1 byte      ; White y coordinate at 22h

; Flat Panel #04
$Chromacity_Enable_04                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_04                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_04                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_04                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_04                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_04                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_04                               1 byte      ; Green x coordinate at 1Dh
$Green_y_04                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_04                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_04                                1 byte      ; Blue y coordinate at 20h
$White_x_04                               1 byte      ; White x coordiante at 21h
$White_y_04                               1 byte      ; White y coordinate at 22h

; Flat Panel #05
$Chromacity_Enable_05                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_05                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_05                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_05                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_05                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_05                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_05                               1 byte      ; Green x coordinate at 1Dh
$Green_y_05                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_05                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_05                                1 byte      ; Blue y coordinate at 20h
$White_x_05                               1 byte      ; White x coordiante at 21h
$White_y_05                               1 byte      ; White y coordinate at 22h

; Flat Panel #06
$Chromacity_Enable_06                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_06                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_06                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_06                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_06                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_06                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_06                               1 byte      ; Green x coordinate at 1Dh
$Green_y_06                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_06                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_06                                1 byte      ; Blue y coordinate at 20h
$White_x_06                               1 byte      ; White x coordiante at 21h
$White_y_06                               1 byte      ; White y coordinate at 22h

; Flat Panel #07
$Chromacity_Enable_07                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_07                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_07                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_07                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_07                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_07                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_07                               1 byte      ; Green x coordinate at 1Dh
$Green_y_07                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_07                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_07                                1 byte      ; Blue y coordinate at 20h
$White_x_07                               1 byte      ; White x coordiante at 21h
$White_y_07                               1 byte      ; White y coordinate at 22h

; Flat Panel #08
$Chromacity_Enable_08                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_08                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_08                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_08                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_08                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_08                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_08                               1 byte      ; Green x coordinate at 1Dh
$Green_y_08                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_08                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_08                                1 byte      ; Blue y coordinate at 20h
$White_x_08                               1 byte      ; White x coordiante at 21h
$White_y_08                               1 byte      ; White y coordinate at 22h

; Flat Panel #09
$Chromacity_Enable_09                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_09                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_09                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_09                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_09                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_09                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_09                               1 byte      ; Green x coordinate at 1Dh
$Green_y_09                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_09                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_09                                1 byte      ; Blue y coordinate at 20h
$White_x_09                               1 byte      ; White x coordiante at 21h
$White_y_09                               1 byte      ; White y coordinate at 22h

; Flat Panel #10
$Chromacity_Enable_10                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_10                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_10                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_10                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_10                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_10                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_10                               1 byte      ; Green x coordinate at 1Dh
$Green_y_10                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_10                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_10                                1 byte      ; Blue y coordinate at 20h
$White_x_10                               1 byte      ; White x coordiante at 21h
$White_y_10                               1 byte      ; White y coordinate at 22h

; Flat Panel #11
$Chromacity_Enable_11                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_11                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_11                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_11                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_11                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_11                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_11                               1 byte      ; Green x coordinate at 1Dh
$Green_y_11                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_11                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_11                                1 byte      ; Blue y coordinate at 20h
$White_x_11                               1 byte      ; White x coordiante at 21h
$White_y_11                               1 byte      ; White y coordinate at 22h

; Flat Panel #12
$Chromacity_Enable_12                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_12                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_12                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_12                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_12                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_12                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_12                               1 byte      ; Green x coordinate at 1Dh
$Green_y_12                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_12                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_12                                1 byte      ; Blue y coordinate at 20h
$White_x_12                               1 byte      ; White x coordiante at 21h
$White_y_12                               1 byte      ; White y coordinate at 22h

; Flat Panel #13
$Chromacity_Enable_13                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_13                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_13                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_13                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_13                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_13                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_13                               1 byte      ; Green x coordinate at 1Dh
$Green_y_13                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_13                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_13                                1 byte      ; Blue y coordinate at 20h
$White_x_13                               1 byte      ; White x coordiante at 21h
$White_y_13                               1 byte      ; White y coordinate at 22h

; Flat Panel #14
$Chromacity_Enable_14                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_14                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_14                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_14                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_14                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_14                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_14                               1 byte      ; Green x coordinate at 1Dh
$Green_y_14                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_14                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_14                                1 byte      ; Blue y coordinate at 20h
$White_x_14                               1 byte      ; White x coordiante at 21h
$White_y_14                               1 byte      ; White y coordinate at 22h

; Flat Panel #15
$Chromacity_Enable_15                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_15                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_15                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_15                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_15                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_15                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_15                               1 byte      ; Green x coordinate at 1Dh
$Green_y_15                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_15                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_15                                1 byte      ; Blue y coordinate at 20h
$White_x_15                               1 byte      ; White x coordiante at 21h
$White_y_15                               1 byte      ; White y coordinate at 22h

; Flat Panel #16
$Chromacity_Enable_16                     1 bit       ; enable or disable the chromacity bit
$Override_EDID_Data_16                    1 bit       ; Override the chromaticity bit
SKIP                                      6 bits      ; Reserved bits
$Red_Green_16                             1 byte      ; Red/green chormaticity coordinates at 19h
$Blue_White_16                            1 byte      ; Blue/white chromatiity coordinates at 1Ah
$Red_x_16                                 1 byte      ; Red x coordinate at 1Bh
$Red_y_16                                 1 byte      ; Red y coordinate at 1Ch
$Green_x_16                               1 byte      ; Green x coordinate at 1Dh
$Green_y_16                               1 byte      ; Green y ccoordinate at 1Eh
$Blue_x_16                                1 byte      ; Blue x coordinate at 1Fh
$Blue_y_16                                1 byte      ; Blue y coordinate at 20h
$White_x_16                               1 byte      ; White x coordiante at 21h
$White_y_16                               1 byte      ; White y coordinate at 22h

;==============================================================================
; Block 51 - Fixed Mode
;------------------------------------------------------------------------------

SKIP                                      3 bytes     ; Skip block ID and size

$Feature_Enable                           1 byte      ; Enable or disable the feature
$X_res                                    4 bytes     ; X resolution
$Y_res                                    4 bytes     ; Y resolution

EndStruct

;==============================================================================
; List Definitions
;------------------------------------------------------------------------------

List    &Pwr_Pref_List
  Selection       0x01,       "1 - Maximum Quality with No DPST"
  Selection       0x02,       "2"
  Selection       0x03,       "3"
  Selection       0x04,       "4"
  Selection       0x05,       "5"
  Selection       0x06,       "6 - Maximum Battery"
EndList

; This is the list for the selection of the Device Class
List    &Int_EFP_Device_Type_List
  Selection       0x0000,     "No Device"
  Selection       0x68C6,     "Integrated DisplayPort Only"
  Selection       0x60D6,     "Integrated DisplayPort with HDMI/DVI Compatible"
  Selection       0x68D6,     "Integrated DisplayPort with DVI Compatible"
  Selection       0x60D2,     "Integrated HDMI/DVI"
  Selection       0x68D2,     "Integrated DVI Only"
EndList

; This is the list for the selection of the Device Class for DDI-E only.
List    &Int_EFP4_Device_Type_List
  Selection       0x0000,     "No Device"
  Selection       0x68C6,     "Integrated DisplayPort Only"
EndList

List    &Disabled_Enabled_List
  Selection       0,          "Disabled"
  Selection       1,          "Enabled"
EndList

List    &Int_EFP_Port_List
  Selection       0x00,       "N/A"
  Selection       0x01,       "HDMI-B"
  Selection       0x02,       "HDMI-C"
  Selection       0x03,       "HDMI-D"
  Selection       0x07,       "DisplayPort-B"
  Selection       0x08,       "DisplayPort-C"
  Selection       0x09,       "DisplayPort-D"
EndList

List    &Int_EFP4_Port_List
  Selection       0x00,       "N/A"
  Selection       0x0B,       "DisplayPort-E"
EndList

List    &eDP_Port_List
  Selection       0x0A,       "DisplayPort-A"
  ;Selection      0x09,       "DisplayPort-D"
EndList

List    &Int_DP_AUX_Channel_List
  Selection       0x00,       "N/A"
  Selection       0x40,       "AUX Channel A"
  Selection       0x10,       "AUX Channel B"
  Selection       0x20,       "AUX Channel C"
  Selection       0x30,       "AUX Channel D"
EndList

List    &Int_eDP_AUX_Channel_List
  Selection       0x40,       "AUX Channel A"
  ;Selection      0x30,       "AUX Channel D"
EndList

List    &GPIO_Pin_List
  Selection       0x00,       "N/A"
  Selection       0x05,       "Integrated HDMI-B DDC GPIO Pins"
  Selection       0x04,       "Integrated HDMI-C DDC GPIO Pins"
  Selection       0x06,       "Integrated HDMI-D DDC GPIO Pins"
EndList    

List    &GMBus_Speed_List
  Selection       0x01,       "50 KHz"
  Selection       0x00,       "100 KHz"
  Selection       0x02,       "400 KHz"
  Selection       0x03,       "1 MHz"
EndList

List    &Inv_Type_List
  Selection       0x00,       "None/External"
  Selection       0x02,       "PWM"
EndList

List    &Inv_Polarity_List
  Selection       0x00,       "Normal"
  Selection       0x01,       "Inverted"
EndList

List    &LVDS_Config_List
  Selection       0x00,       "No Local Flat Panel"
  Selection       0x03,       "eDP (LFP Driven by Int-DisplayPort Encoder)"
EndList

List    &No_Yes_List
  Selection       0,          "No"
  Selection       1,          "Yes"
EndList

List    &Yes_No_List
  Selection       0,          "Yes"
  Selection       1,          "No"
EndList

List    &Off_On_List
  Selection       0,          "Off"
  Selection       1,          "On"
EndList

List    &OS_Driver_List
  Selection       0,          "OS Default Algorithm"
  Selection       1,          "Driver Algorithm"
EndList

List    &eDP_Panel_Color_Depth_List
  Selection       0x00,       "18-bit Color Depth"
  Selection       0x01,       "24-bit Color Depth"
  Selection       0x02,       "30-bit Color Depth"
  Selection       0x03,       "36-bit Color Depth"
EndList

List    &eDP_Link_DataRate_List
  Selection       0x00,       "1.62 Gbps"
  Selection       0x01,       "2.70 Gbps"
  Selection       0x02,       "5.40 Gbps"
EndList

List    &eDP_Link_LaneCount_List
  Selection       0x00,       "x1"
  Selection       0x01,       "x2"
  Selection       0x03,       "x4"
EndList

List    &DP_eDP_Link_PreEmp_List
  Selection       0x00,       "Level-0"
  Selection       0x01,       "Level-1"
  Selection       0x02,       "Level-2"
  Selection       0x03,       "Level-3"
EndList

List    &eDP_Link_VSwing_List
  Selection       0x00,       "Swing-0"
  Selection       0x01,       "Swing-1"
  Selection       0x02,       "Swing-2"
  Selection       0x03,       "Swing-3"
EndList

List    &DP_Link_VSwing_List
  Selection       0x00,       "Swing-0"
  Selection       0x01,       "Swing-1"
  Selection       0x02,       "Swing-2"
EndList

List    &IBoost_Magnitude_List
  Selection       0,          "0x1"
  Selection       1,          "0x3"
  Selection       2,          "0x7"
EndList

List    &Panel_List
  Selection       0x00,       "PANEL #01"
  Selection       0x01,       "PANEL #02"
  Selection       0x02,       "PANEL #03"
  Selection       0x03,       "PANEL #04"
  Selection       0x04,       "PANEL #05"
  Selection       0x05,       "PANEL #06"
  Selection       0x06,       "PANEL #07"
  Selection       0x07,       "PANEL #08"
  Selection       0x08,       "PANEL #09"
  Selection       0x09,       "PANEL #10"
  Selection       0x0A,       "PANEL #11"
  Selection       0x0B,       "PANEL #12"
  Selection       0x0C,       "PANEL #13"
  Selection       0x0D,       "PANEL #14"
  Selection       0x0E,       "PANEL #15"
  Selection       0x0F,       "PANEL #16"
EndList

List    &eDP_VSwing_Preemph_table_List
  Selection       0x00,       "Low Power VSwing/Pre-Emphasis Table"
  Selection       0x01,       "Default VSwing/Pre-Emphasis Table"
EndList

List    &Under_Over_List
  Selection       0x0,        "Enable Underscan and Overscan modes"
  Selection       0x1,        "Enable only overscan modes"
  Selection       0x2,        "Enable only underscan modes"
EndList

List    &DPS_Panel_Type_List
  Selection       0x00,       "Static DRRS"
  Selection       0x02,       "Seamless"
EndList

List    &Blt_Control_Type_List
  Selection       0x01,       "CCFL Backlight"
  Selection       0x02,       "LED Backlight"
EndList

List    &Hdmi_LS_List
  Selection       0x00,       "400mV 0.0dB"
  Selection       0x01,       "400mV 3.5dB"
  Selection       0x02,       "400mV 6.0dB"
  Selection       0x03,       "450mV 0.0dB"
  Selection       0x04,       "600mV 0.0dB"
  Selection       0x05,       "600mV 2.5dB"
  Selection       0x06,       "600mV 4.5dB"
  Selection       0x07,       "800mV 0.0dB"
  Selection       0x08,       "800mV 2.0dB"
  Selection       0x09,       "1000mV 2.0dB"
  Selection       0x0A,       "1200mV 0.0dB"
EndList

List    &wait_line_link
  Selection       0x00,       "0 lines to wait"
  Selection       0x01,       "2 lines to wait"
  Selection       0x02,       "4 lines to wait"
  Selection       0x03,       "8 lines to wait"
EndList

List    &PrimaryDisplayList
  Selection       0x08,       "LFP"
  Selection       0x04,       "EFP"
  Selection       0x40,       "EFP2"
  Selection       0x20,       "EFP3"
  Selection       0x10,       "EFP4"
  Selection       0x00,       "None"
EndList

List    &SecondaryDisplayList
  Selection       0x04,       "EFP"
  Selection       0x40,       "EFP2"
  Selection       0x20,       "EFP3"
  Selection       0x10,       "EFP4"
  Selection       0x00,       "None"
EndList

List    &Hdmi2SupportOptions
  Selection       0x00,       "Disabled"
  Selection       0x01,       "Enabled"
EndList

List    &PsrWakeupTimeOptions
  Selection       0x00,       "500 usec"
  Selection       0x01,       "100 usec"
  Selection       0x02,       "2.5 msec"
  Selection       0x03,       "0 (Skip)"
EndList

List    &Pwm_Source_List
  ; Selection       0x0,        "PWM From PMIC"
  ; Selection       0x1,        "PWM From LPSS"
  Selection       0x2,        "PWM From Display Engine"
  ; Selection       0x3,        "PWM From LCD Panel"
  Selection       0x4,        "Panel driver interface (OLED)"
EndList

;==============================================================================
; Page Definitions
;------------------------------------------------------------------------------

BeginInfoBlock
PPVer    "3.00"
Image EOF Thru EOF At EOF
EndInfoBlock

;==============================================================================
; Page - Revision History
;------------------------------------------------------------------------------
Page      "VBT Information"
  Title     "PLATFORM : Skylake/Kabylake"
  Title     "VBT version: 205"

  #IF       $LVDS_Config == 3
    Title     "Supported LFP type: eDP"
  #ELSE
    Title     "Supported LFP type: No LFP"
  #ENDIF
EndPage   ; Revision History

;==============================================================================
; Page - General Platform Configuration
;------------------------------------------------------------------------------
Page      "General Platform Configuration"

  Combo     $Embedded_Platform, "Embedded Platform: ", &No_Yes_List,
  Help      "This feature allows a selectable option to determine whether "
            "the platform is embedded design or not."

  Combo     $bmp_Dynamic_CdClock_Supported, "Dynamic CD Clock Support: ", &Disabled_Enabled_List,
  Help      "Enabling this feature configures optimal CD Clock frequency at run time .\n "

  Combo     $Kvmr_Session_Enable, "KVMR Session/Fake DVI Display Support: ", &Disabled_Enabled_List,
  Help      "When enabled, GOP and Gfx driver will keep a display pipe enable even if no displays are attached.\n"
            "When no displays are attached, GOP or Gfx driver will check VBT settings for EFP1/2/3 for DVI support.\n"
            "If any EFP setting supports DVI display type, GOP/driver will enable that port.\n"
            "If none of the EFP settings support DVI display type, GOP/driver will enable DVI on port-B by default."

EndPage   ; General platform Configuration

;==============================================================================
; Page - UEFI GOP Driver Configuration
;------------------------------------------------------------------------------
Page      "UEFI GOP Driver Configuration"

  Combo     $Hotplug_Support_Enb, "Hot Plug Support:", &Disabled_Enabled_List,
  Help      "This feature is to enable/disable Hot Plug Support for EFP displays in GOP driver."

  Title     "Child Device Configuration"
  Link      "Child Device List", "Child Device List"

  Title     "Fixed Mode"
  Link      "Fixed Mode Feature", "Fixed Mode Feature"

  ;==============================================================================
  ; Page - Child Device List
  ;------------------------------------------------------------------------------

  Page      "Child Device List"
    Link      "Close Table" , ".."
    Title     "A child device is a combination of one or more displays. Select the child devices that the GOP driver should enumerate if detected"
    Title     "Note: The child devices are listed here in decreasing order of priority. In case the system BIOS does not specify the child device to start, then GOP driver selects the highest priority child device"

    Title     "Child Device 1"
    Combo     $ChildDevice1Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice1Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 2"
    Combo     $ChildDevice2Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice2Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 3"
    Combo     $ChildDevice3Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice3Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 4"
    Combo     $ChildDevice4Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice4Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 5"
    Combo     $ChildDevice5Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice5Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 6"
    Combo     $ChildDevice6Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice6Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 7"
    Combo     $ChildDevice7Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice7Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 8"
    Combo     $ChildDevice8Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice8Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 9"
    Combo     $ChildDevice9Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice9Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 10"
    Combo     $ChildDevice10Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice10Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 11"
    Combo     $ChildDevice11Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice11Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 12"
    Combo     $ChildDevice12Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice12Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 13"
    Combo     $ChildDevice13Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice13Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 14"
    Combo     $ChildDevice14Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice14Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 15"
    Combo     $ChildDevice15Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice15Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"

    Title     " "
    Title     "Child Device 16"
    Combo     $ChildDevice16Primary, "\tPrimary display: " , &PrimaryDisplayList,
    Help      "Primary Display\r\n"
    Combo     $ChildDevice16Secondary, "\tSecondary display: " , &SecondaryDisplayList,
    Help      "Secondary Display\r\n"
  EndPage   ; "Child Device List"

  ;============================================================================
  ; Page - Fixed Mode Configuration
  ;----------------------------------------------------------------------------

  Page      "Fixed Mode Feature"
    Link      "Close Table", ".."

    Combo     $Feature_Enable, "Enable Feature:",  &No_Yes_List,
    Help      "Fixed Mode Feature allows user to fix a mode during POST such that only that particular mode will be always set."
              "This field specifies if user wants to enable/disable the feature."
              "When enabled user is expected to provide a valid input."

    EditNum   $X_res, "Horizontal Pixels:", DEC,
    Help      "This value specifies the horizontal pixels of the mode."
              "It should be always less than or equal to the native horizontal resolution."

    EditNum   $Y_res, "Vertical Pixels:", DEC,
    Help      "This value specifies the vertical pixels of the mode."
              "It should be always less than or equal to the native vertical resolution."

  EndPage

EndPage   ; "UEFI GOP Driver Configuration"

;============================================================================
; Page - Windows Graphics driver Configuration
;----------------------------------------------------------------------------
Page      "Windows Graphics driver Configuration"

  Link      "General Features" , "General Features"
  Link      "Display Features" , "Display Features"
  Link      "Power Conservation" , "Power Conservation"

  Page      "General Features"
    Link      "Close Table" , ".."

    EditNum   $VBT_Customization_Version, "VBT Customization Version:", DEC,
    Help      "This feature allows the OEM to have a customized VBT version number. "
              "The permissible values for VBT Customization version is from 0 to 255."

    Combo     $Disable_DisplayEnum, "Display subsystem disabled:", &No_Yes_List,
    Help      "This option allows windows driver to be aware that display subsystem is not needed. "
              "Driver could choose not to activate any display hardware if this bit is set. "
              "However this is only valid if there’s no LFP on the system or no Force projectable connector. "
              "Please see driver documentation for detailed driver behaviour."

  EndPage   ; General Features"

  Page      "Display Features"
    Link      "Close Table" , ".."

    Combo     $CUI_Maintain_Aspect, "Enable 'Maintain Aspect Ratio':", &No_Yes_List,
    Help      "This feature allows the OEM to enable or disable the 'Maintain Aspect Ratio' feature. "
              "When the option is set to Yes, the feature will be enabled and CUI will show "
              "for end user selection 'Maintain Aspect Ratio'. When the option is set to No, "
              "the complete 'Maintain Aspect Ratio' feature will be disabled."

    Title     "Legacy Monitor Mode Limit:"

    EditNum   $Legacy_Monitor_Max_X, "    Maximum X Resolution (Pixels):", DEC,
    Help      "This feature allows the limiting of selectable display modes "
              "when a legacy monitor is detected. The maximum resolution is specified by "
              "a maximum number of horizontal active pixels.\r\n"
              "Note: A legacy monitor is defined as a monitor with no DDC available."

    EditNum   $Legacy_Monitor_Max_Y, "    Maximum Y Resolution (Pixels):", DEC,
    Help      "This feature allows the limiting of selectable display modes "
              "when a legacy monitor is detected.  The maximum resolution is specified by "
              "a maximum number of vertical active pixels.\r\n"
              "Note: A legacy monitor is defined as a monitor with no DDC available."

    EditNum   $Legacy_Monitor_Max_RR, "    Maximum Refresh Rate (Hz):", DEC,
    Help      "This feature allows the limiting of selectable display modes "
              "when a legacy monitor is detected.  The maximum refresh rate "
              "is specified in Hz.\r\n"
              "Note: A legacy monitor is defined as a monitor with no DDC available."

    Title     "Rotation Configuration:"

    Combo     $Rot_Enable, "    Enable Rotation:", &No_Yes_List,
    Help      "This feature when set to yes, will allow for rotation. "
              "Otherwise, when the feature is set to no, "
              "the rotation functionality will be disabled within the driver."

  EndPage   ; Display features

  Page      "Power Conservation"
    Link      "Close Table" , ".."

    Title     "    "

    Combo     $PC_Fields_Enable, "  PC Features Control Options", &Disabled_Enabled_List,
    Help      "This feature determines the validity of the following PC Features Control Options.\r\n\r\n"
              "1.  Intel® Rapid Memory Power Management (RMPM)\r\n"
              "2.  Intel® Smart 2D Display Technology (S2DDT)\r\n"
              "3.  Intel® Display Power Saving Technology (DPST) (Mobile only)\r\n"
              "4.  DxgkDDI Backlight Control (DxgkDdiBLC) (Mobile only)\r\n"
              "5.  Intel® Automatic Display Brightness (ADB) (Mobile only)\r\n"
              "6.  Intel® Display Refresh Rate Switching (DRRS) (Mobile only)\r\n"
              "7.  Graphics Render Standby (RS)\r\n"
              "8.  Intel® Turbo Boost Technology\r\n"
              "9.  Dynamic Frames Per Second (DFPS)\r\n"
              "10. Dynamic Media Refresh Rate Switching (DMRRS)\r\n"
              "11. Assertive Display Technology (ADT)\r\n\r\n"
              "Note: Enable and Save the changes to display all the PC Features Control Options\r\n"

    Combo     $PM_RMPM_Enable, "\tIntel® Rapid Memory Power Management (RMPM)", &Disabled_Enabled_List,
    Help      "This feature determines whether Intel® Rapid Memory Power Management (RMPM) is to be enabled. "

    Combo     $PM_S2DDT_Enable, "\tIntel® Smart 2D Display Technology (S2DDT)", &Disabled_Enabled_List,
    Help      "This feature determines whether Intel® Smart 2D Display Technology (S2DDT) is to be enabled. "

    Combo     $PM_DPST_Enable, "\tIntel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
    Help      "This feature determines whether the Intel® Display Power Savings Technology (DPST) is enabled or disabled. "
              "Intel® DPST is a display power savings technology that changes the intensity of colors in order to conserve backlight power."
              "\r\n\r\nNote: This technology is only active when the system is running in battery mode and "
              "the LFP is the only active display device."

    Combo     $BIA_Aggress_Level, "\t\tDPST Aggressiveness Level (Mobile only)", &Pwr_Pref_List,
    Help      "This feature defines the Intel® Display Power Saving Technology aggressiveness level if and only if "
              "the feature Intel® Display Power Saving Technology is enabled."   
              "\r\n\r\nThe following are the definitions for each level:"
              "\r\n1 - Maximum Quality - shall use no DPST "
              "\r\n2 - Provides  the user the maximum brightness for their embedded Local Flat Panel (LFP)while DPST is in use"
              "\r\n3 - This level defines maximum amount of brightness with minimal power savings"
              "\r\n4 - This level defines an intermediate value for brightness amount"
              "\r\n5 - This level defines an intermediate value for the brightness amount"
              "\r\n6 - Maximum Battery - Provided the user with the minimum amount of "
              "brightness capable for their LFP with the maximum power savings"

    Combo     $PM_BLC_Enable, "\tDxgkDDI Brightness Control Method (Mobile only)", &Disabled_Enabled_List,
    Help      "This option determines whether the Vista, Win7, and future version DxgkDDI LFP Brightness Control method is to be enabled. "

    Combo     $PM_ADB_Enable, "\tIntel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
    Help      "This feature determines whether Intel® Automatic Display Brightness is to be enabled. "
              "Intel® Automatic Display Brightness adjusts the brightness of the embedded Local Flat Panel (LFP) "
              "depending on the current ambient light environment. "
              "When enabled, the driver and VBIOS will control the backlight brightness of the LFP "
              "depending on the ambient environment if and only if the LFP is the only active display. "
              "When disabled, the driver will perform no action."

    Link      "ADB Response Data (Mobile only)" , "ADB Response Data (Mobile only)"

    Combo     $PM_DRRS_Enable, "\tIntel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
    Help      "This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be enabled."

    Combo     $PM_RS_Enable, "\tGraphics Render Standby (RS)", &Disabled_Enabled_List,
    Help      "This feature determines whether Graphics Render Standby (RS)is to be enabled."

    Combo     $PM_Turbo_Enable, "\tIntel® Turbo Boost Technology", &Disabled_Enabled_List,
    Help      "This feature determines whether Intel® Turbo Boost Technology is to be enabled."

    Combo     $Panel_Self_Refresh, "\tPanel Self Refresh (PSR)", &Disabled_Enabled_List,
    Help      "This feature determines whether Panel Self Refresh (PSR) feature is to be enabled."

    Combo     $Dynamic_FPS_Enable, "\tDynamic Frames Per Second (DFPS)", &Disabled_Enabled_List,
    Help      "This feature determines whether Dynamic Frames Per Second is to be enabled."

    Combo     $DMRRS, "\tDynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
    Help      "This feature determines whether Dynamic media refresh rate switching is to be enabled."

    Combo     $ADT, "\tAssertive Display Technology Enable/Disable", &Disabled_Enabled_List,
    Help      "This feature determines whether Assertive display technology is to be enabled. "

    Page      "ADB Response Data (Mobile only)"
      Link      "Close Table" , ".."

      Table     $ALS_Response_Data " ADB Response Data (Mobile only)",
      Column    "Backlight Adjust", 2 bytes, EHEX
      Column    "Lux", 2 bytes, EHEX,
      Help      "This feature defines values used to calibrate the Intel® Automatic Display Brightness policy's "
                "response to account for specific hardware implementation details such as sensor placement and optics. "
                "Up to five points can be specified, where each point indicates a given ambient light illuminance "
                "to display luminance mapping specified as (<%BacklightAdjust>, <Lux>).  Points should be "
                "listed in monotonically increasing order by ambient light illuminance (lux). "
                "A minimum of two points are required (min and max)."
    EndPage   ; "ADB Response Data"
  EndPage   ; Power Conservation
EndPage   ; "Windows Graphics driver Configuration"

;==============================================================================
; Page - Display Configurations
;------------------------------------------------------------------------------
Page      "Integrated Display Configuration"
  Title     "Integrated DP, HDMI, DVI, eDP Configuration"

  Link      "LFP Configuration", "LFP Configuration"
  Link      "Integrated DisplayPort/HDMI Configuration with External Connectors", "Integrated DisplayPort/HDMI Configuration with External Connectors"

  ;==============================================================================
  ; Page - LFP Configuration
  ;----------------------------------------------------------------------------

  Page      "LFP Configuration"
    Link      "Close Table", ".."
    Combo     $LVDS_Config , "Active Local Flat Panel Configuration", &LVDS_Config_List,
    Help      "This feature is for configuring LFP usage.\r\n"
              "Note: To enable 4 lane eDP panels, make sure that the EFP4 settings in VBT has no device."

    Title     "    "
    Combo     $Int_eDP_Port, "Select Output port: ", &eDP_Port_List,
    Help      "This feature, when enabled, will activate support for an eDP. "
              "Driver also uses the same data for enabling eDP on the selected port.\r\n\r\n"
              "Note: For both mobile and desktop SKL/KBL boards, eDP is supported on Port A only."

    Combo     $Int_LFP_AUX_Channel, "Select AUX Channel: ", &Int_eDP_AUX_Channel_List,
    Help      "This feature specifies the AUX Channel for embedded-DisplayPort. "
              "This field is valid only if integrated eDP is selected for Device Type."

    Title     "    "
    Combo     $bmp_Panel_type, "Select Panel Type:", &Panel_List,
    Help      "This feature selects the Local Flat Panel (LFP) the GOP and driver is to enable.\r\n\r\n"
              "Default LFP parameter values:\r\n"
              "\tPANEL #01: 640x480 LFP\r\n"
              "\tPANEL #02: 800x600 LFP\r\n"
              "\tPANEL #03: 1024x768 LFP\r\n"
              "\tPANEL #04: 1280x1024 LFP\r\n "
              "\tPANEL #05: 1400x1050 Reduced Blanking LFP\r\n"
              "\tPANEL #06: 1400x1050 Non-Reduced Blanking LFP\r\n"
              "\tPANEL #07: 1600x1200 LFP\r\n"
              "\tPANEL #08: 1280x768 LFP\r\n"
              "\tPANEL #09: 1680x1050 LFP\r\n"
              "\tPANEL #10: 1920x1200 LFP\r\n"
              "\tPANEL #11: 1440x900 LFP\r\n"
              "\tPANEL #12: 1600x900 LFP\r\n"
              "\tPANEL #13: 1024x768 LFP\r\n"
              "\tPANEL #14: 1280x800 LFP\r\n"
              "\tPANEL #15: 1920x6108 LFP\r\n"
              "\tPANEL #16: 2048x1536"

    Combo     $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List,
    Help      "This feature, when enabled, will activate support for a LFP with an EDID. "
              "The GOP and driver will load the EDID and "
              "use its data to set appropriate timing on current panel. "
              "If disabled, there will be no attempt to read an EDID and "
              "other methods will be used to set panel timing."


    Combo     $LFP_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List,
    Help      "This feature, when enabled, will set lane reversal bit for Selected Port "

    Combo     $LFP_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List,
    Help      "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels"

    Combo     $Int_LFP_Dp_Boost_Magnitude, "\tIBoost Magnitude: ", &IBoost_Magnitude_List,
    Help      "This field is applicable only if IBoost is enabled for the selected port."
              "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7"

    ; Combo     $180_Deg_Rotation_Enable, "Enable 180 Degree Rotation:", &No_Yes_List,
    ; Help      "This feature when set to yes, will enable 180 Degree rotation "
    ;           "otherwise, the rotation functionality will be disabled."

    Combo     $Int_LFP_Dual_Pipe_Ganged_Enable, "Dual Port Ganged Support for eDP: ", &Disabled_Enabled_List,
    Help      "This feature allows for configuring two different ports to be used for a single eDP panel.\n"
              "When enabled, the end user can specify a slave port to be connected along with DDI-A to enable a higher resolution eDP panel.\n"
              "When disabled, eDP display will always use DDI-A"

    Combo     $Int_LFP_Slave_Dvo_Port, "\tSlave Port for Dual Port Ganged eDP Display: ", &Int_EFP_Port_List,
    Help      "This field provides the slave port to be used along with master eDP port in case of dual port ganged support for eDP.\n"
              "This field will be ignored by the software if dual port ganged support for eDP is disabled."

    Title     "    "

    Link      "Panel #01 ", "Panel #01 "
    Link      "Panel #02 ", "Panel #02 "
    Link      "Panel #03 ", "Panel #03 "
    Link      "Panel #04 ", "Panel #04 "
    Link      "Panel #05 ", "Panel #05 "
    Link      "Panel #06 ", "Panel #06 "
    Link      "Panel #07 ", "Panel #07 "
    Link      "Panel #08 ", "Panel #08 "
    Link      "Panel #09 ", "Panel #09 "
    Link      "Panel #10 ", "Panel #10 "
    Link      "Panel #11 ", "Panel #11 "
    Link      "Panel #12 ", "Panel #12 "
    Link      "Panel #13 ", "Panel #13 "
    Link      "Panel #14 ", "Panel #14 "
    Link      "Panel #15 ", "Panel #15 "
    Link      "Panel #16 ", "Panel #16 "

    ;==============================================================================
    ; Page - Panel #01 (640x480 LVDS) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #01 "
      EditText  $Panel_Name_01, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_01, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_01, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_01, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_01, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "

      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "PSR feature" , "PSR feature"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_01, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_01 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_01 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_01, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_01, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_01, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_01, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_01, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_01, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_01, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_01, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_01, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_01, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_01, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_01, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_01, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_01, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_01, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_01, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_01, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_01, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"

        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_01, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"

        Combo     $eDP_Fast_Link_Training_Supported_01, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_01, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_01, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_01, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_01, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_01, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_01, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_01, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_01, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_01, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_01, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_01, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_01, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_01, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_01, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_01, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_01, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_01, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_01, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage   ; Panel #01

    ;==============================================================================
    ; Page - Panel #02 (800x600 LVDS) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #02 "
      EditText  $Panel_Name_02, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_02, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_02, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_02, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_02, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC02, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_02, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "PSR feature" ,"PSR feature"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_02, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_02 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_02 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_02, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_02, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_02, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_02, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_02, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_02, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_02, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_02, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_02, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_02, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_02, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_02, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_02, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_02, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_02, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_02, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_02, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_02, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"
        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_02, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"

        Combo     $eDP_Fast_Link_Training_Supported_02, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_02, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_02, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_02, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_02, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_02, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_02, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_02, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_02, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_02, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_02, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_02, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_02, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_02, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_02, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_02, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_02, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_02, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_02, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage

    ;==============================================================================
    ; Page - Panel #03 (1024x768 LVDS) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #03 "
      EditText  $Panel_Name_03, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_03, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_03, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_03, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_03, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC03, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_03, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "PSR feature" ,"PSR feature"
      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_03, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_03 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_03 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_03, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_03, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_03, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_03, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_03, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_03, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_03, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_03, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_03, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_03, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_03, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_03, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_03, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_03, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_03, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_03, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_03, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_03, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"
        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_03, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"

        Combo     $eDP_Fast_Link_Training_Supported_03, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_03, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_03, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_03, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_03, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_03, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_03, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_03, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_03, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo   $PSR_TP1_WaitTime_03, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_03, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_03, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_03, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_03, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_03, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_03, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_03, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_03, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_03, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage

    ;==============================================================================
    ; Page - Panel #04 (1280x1024 LVDS) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #04 "
      EditText  $Panel_Name_04, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_04, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_04, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_04, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_04, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC04, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_04, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "PSR feature" ,"PSR feature"
      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_04, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_04 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_04 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_04, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_04, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_04, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_04, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_04, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_04, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_04, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_04, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_04, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_04, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_04, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_04, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_04, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_04, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_04, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_04, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_04, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_04, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"
        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_04, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"

        Combo     $eDP_Fast_Link_Training_Supported_04, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_04, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_04, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_04, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_04, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_04, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_04, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_04, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_04, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_04, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_04, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_04, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_04, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_04, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_04, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_04, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_04, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_04, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_04, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage

    ;==============================================================================
    ; Page - Panel #05 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #05 "
      EditText  $Panel_Name_05, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_05, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_05, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_05, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_05, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC05, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_05, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "PSR feature" ,"PSR feature"
      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_05, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_05 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_05 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_05, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_05, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_05, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_05, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_05, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_05, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_05, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_05, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_05, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_05, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_05, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_05, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_05, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_05, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_05, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_05, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_05, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_05, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"
        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_05, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"

        Combo     $eDP_Fast_Link_Training_Supported_05, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_05, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_05, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_05, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_05, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_05, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_05, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_05, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_05, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_05, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo   $PSR_TP_2_3_WaitTime_05, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_05, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_05, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_05, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_05, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_05, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_05, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_05, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_05, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature

    EndPage

    ;==============================================================================
    ; Page - Panel #06 (1400x1050) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #06 "
      EditText  $Panel_Name_06, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_06, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_06, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_06, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_06, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_06, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "PSR feature" ,"PSR feature"

      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_06, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_06 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_06 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_06, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_06, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_06, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_06, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_06, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_06, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_06, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_06, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_06, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_06, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_06, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_06, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_06, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_06, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_06, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_06, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_06, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_06, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"
        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_06, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"
        Combo     $eDP_Fast_Link_Training_Supported_06, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_06, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_06, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_06, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_06, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_06, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_06, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_06, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_06, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_06, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_06, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_06, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_06, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_06, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_06, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_06, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_06, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_06, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_06, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage

    ;==============================================================================
    ; Page - Panel #07 (1600x1200) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #07 "
      EditText  $Panel_Name_07, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_07, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_07, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_07, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_07, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC07, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_07, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "PSR feature" ,"PSR feature"
      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_07, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_07 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_07 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_07, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_07, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_07, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_07, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_07, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_07, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_07, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_07, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_07, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_07, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_07, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_07, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_07, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_07, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_07, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_07, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_07, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_07, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"
        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_07, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"
        Combo     $eDP_Fast_Link_Training_Supported_07, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_07, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_07, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_07, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_07, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_07, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_07, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_07, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_07, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_07, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_07, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_07, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_07, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_07, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_07, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_07, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_07, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_07, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_07, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage

    ;==============================================================================
    ; Page - Panel #08 (1280x768) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #08 "
      EditText  $Panel_Name_08, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_08, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_08, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_08, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_08, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC08, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_08, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "PSR feature" ,"PSR feature"
      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_08, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_08 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_08 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_08, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_08, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_08, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_08, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_08, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_08, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_08, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_08, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_08, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_08, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_08, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_08, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_08, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_08, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_08, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_08, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_08, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_08, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"
        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_08, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"

        Combo     $eDP_Fast_Link_Training_Supported_08, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_08, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_08, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_08, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_08, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_08, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_08, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_08, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_08, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_08, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_08, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_08, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_08, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_08, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_08, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_08, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_08, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_08, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_08, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage

    ;==============================================================================
    ; Page - Panel #09 (1680x1050) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #09 "
      EditText  $Panel_Name_09, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_09, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_09, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_09, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_09, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC09, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_09, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_09, "  BackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "PSR feature" ,"PSR feature"
      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_09, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_09 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_09 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_09, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_09, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_09, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_09, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_09, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_09, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_09, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_09, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_09, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_09, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_09, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_09, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_09, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_09, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_09, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_09, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_09, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_09, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"
        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_09, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"
        Combo     $eDP_Fast_Link_Training_Supported_09, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_09, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_09, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_09, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_09, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_09, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_09, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_09, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_09, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_09, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_09, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_09, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_09, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_09, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_09, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_09, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_09, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_09, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_09, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage

    ;==============================================================================
    ; Page - Panel #10 (1920x1200) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #10 "
      EditText  $Panel_Name_10, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_10, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_10, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_10, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_10, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC10, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_10, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "PSR feature" ,"PSR feature"
      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_10, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_10 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_10 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_10, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_10, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_10, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_10, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_10, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_10, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_10, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_10, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_10, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_10, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_10, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_10, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_10, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_10, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_10, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_10, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_10, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_10, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"
        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_10, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"
        Combo     $eDP_Fast_Link_Training_Supported_10, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_10, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_10, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_10, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_10, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_10, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_10, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_10, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_10, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_10, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_10, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_10, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_10, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_10, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_10, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_10, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_10, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_10, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_10, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage

    ;==============================================================================
    ; Page - Panel #11 (Reserved) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #11 "
      EditText  $Panel_Name_11, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_11, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_11, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_11, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_11, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC11, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_11, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "PSR feature" ,"PSR feature"
      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_11, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_11 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_11 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_11, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_11, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_11, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_11, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_11, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_11, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_11, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_11, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_11, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_11, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_11, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_11, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_11, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_11, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_11, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_11, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_11, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_11, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"
        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_11, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"
        Combo     $eDP_Fast_Link_Training_Supported_11, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_11, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_11, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_11, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_11, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_11, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_11, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_11, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_11, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_11, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_11, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_11, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_11, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_11, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_11, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_11, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_11, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_11, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_11, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage

    ;==============================================================================
    ; Page - Panel #12 (Reserved) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #12 "
      EditText  $Panel_Name_12, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_12, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_12, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_12, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_12, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC12, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_12, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "PSR feature" ,"PSR feature"
      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_12, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_12 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_12 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_12, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_12, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_12, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_12, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_12, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_12, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_12, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_12, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_12, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_12, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_12, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_12, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_12, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_12, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_12, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_12, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_12, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_12, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"

        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_12, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"
        Combo     $eDP_Fast_Link_Training_Supported_12, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_12, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_12, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_12, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_12, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_12, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_12, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_12, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_12, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_12, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_12, "  TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_12, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_12, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_12, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_12, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_12, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_12, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_12, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_12, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage

    ;==============================================================================
    ; Page - Panel #13 (Reserved) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #13 "
      EditText  $Panel_Name_13, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_13, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_13, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_13, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_13, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC13, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_13, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "PSR feature" ,"PSR feature"
      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_13, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_13 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_13 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_13, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_13, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_13, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_13, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_13, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_13, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_13, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_13, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_13, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_13, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_13, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_13, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_13, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_13, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_13, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_13, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_13, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_13, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"

        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_13, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"
        Combo     $eDP_Fast_Link_Training_Supported_13, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_13, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_13, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_13, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_13, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_13, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_13, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_13, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_13, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_13, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_13, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_13, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_13, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_13, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_13, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_13, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_13, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_13, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_13, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage

    ;==============================================================================
    ; Page - Panel #14 (1280x800) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #14 "
      EditText  $Panel_Name_14, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_14, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_14, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_14, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_14, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC14, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_14, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "PSR feature" ,"PSR feature"
      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_14, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_14 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_14 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_14, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_14, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_14, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_14, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_14, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_14, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_14, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_14, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_14, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_14, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_14, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_14, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_14, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_14, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_14, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_14, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_14, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_14, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"
        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_14, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"
        Combo     $eDP_Fast_Link_Training_Supported_14, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_14, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_14, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_14, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_14, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_14, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_14, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_14, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_14, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_14, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_14, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_14, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_14, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_14, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_14, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_14, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_14, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_14, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_14, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage

    ;==============================================================================
    ; Page - Panel #15 (1280x600) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #15 "
      EditText  $Panel_Name_15, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_15, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_15, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_15, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_15, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC15, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_15, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "PSR feature" ,"PSR feature"
      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_15, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_15 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_15 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_15, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_15, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_15, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_15, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_15, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_15, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_15, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_15, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_15, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_15, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_15, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_15, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_15, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_15, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_15, "\tBlue_x (Bits 9:2 at 1Fh)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_15, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_15, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_15, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"
        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_15, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"

        Combo     $eDP_Fast_Link_Training_Supported_15, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_15, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_15, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_15, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_15, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_15, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_15, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_15, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_15, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_15, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_15, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_15, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_15, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_15, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_15, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_15, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_15, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_15, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_15, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage

    ;==============================================================================
    ; Page - Panel #16 (Reserved) Flat Panel parameters
    ;------------------------------------------------------------------------------
    Page      "Panel #16 "
      EditText  $Panel_Name_16, "LFP panel name:",
      Help      "This feature defines the LFP panel name, used by driver only. "
                "Panel name can be only of 13 characters maximum and rest of the characters will be truncated."

      EditNum   $Panel_Width_16, "LFP Width:", DEC,
      Help      "This value specifies the LFP pixel width for this panel type."

      EditNum   $Panel_Height_16, "LFP Height:", DEC,
      Help      "This value specifies the LFP pixel height (number of scan lines) for this panel type."

      Combo     $eDP_VSwingPreEmph_16, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help      "This feature selects the VSwing Pre-Emphasis setting table to be used. "
                "For Skylake/Kabylake, based on the selection respective table will be used.\r\n"
                "Tables for Skylake/Kabylake: \r\n"
                "Low Power VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 200mV, 0db \t\t 200mV, 1.5db \t\t 200mV, 6db \t\t 200mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 250mV, 0db \t\t 250mV, 3.5db \t\t 250mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 350mV, 0db \t\t 350mV, 4.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t 800mV,0db \t\t N/A \t\t\t N/A \t\t\t N/A\n"
                "\r\n\r\n"

                "Default VSwing Pre-Emphasis Setting Table:\n"
                "\t\t\t\t\t\t\t\t Pre-Emphasis (db)\n"
                " \t\t DP Applet \t\t Level-0/0dB \t\t Level-1/3.5dB \t\t Level-2/6dB \t\t Level-3/9.5dB\n"
                "Voltage \t\t Level-0/400mV \t\t 400mV, 0db \t\t 400mV, 3.5db \t\t 400mV, 6db \t\t 400mV, 9.5dB \n"
                "Swing \t\t Level-1/600mV \t\t 600mV, 0db \t\t 600mV, 3.5db \t\t 600mV, 6db \t\t N/A\n"
                "(mV) \t\t Level-2/800mV \t\t 800mV, 0db \t\t 800mV, 3.5db \t\t N/A \t\t\t N/A\n"
                "\t\t Level-3/1200mV \t\t N/A \t\t\t N/A \t\t\t N/A \t\t\t N/A\n"

      Combo     $eDP_Panel_Color_Depth_16, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help      "This feature specifies the color depth of eDP panel used."

      TitleB    "eDP Spread Spectrum Clock Features"
      Combo     $Enable_SSC16, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help      "This feature will allow users to disable/enable Spread Spectrum Clock for eDP."

      TitleB    "DPS Panel Type Features (Mobile only)"
      Combo     $DPS_Panel_Type_16, "\tDPS Panel Type:", &DPS_Panel_Type_List,
      Help      "This feature allows OEM to select the DPS Panel Type.\r\n"
                "Intel SDRRS Technology is a feature of the Intel graphics driver which reduces display power.\r\n"
                "SDRRS:- Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience.\r\n"
                "Seamless:-  Allows power savings when on battery mode and "
                "when a lower refresh rate will not adversely impact the user experience."
                "Implements seamless refresh rate switching, which eliminates the screen blink that occurred "
                "during the refresh rate transitions"

      TitleB    "BackLight Technology Type Features (Mobile only)"
      Combo     $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type_List,
      Help      "This feature allows OEM to select the Backlight Technology."

      Title     " "
      Link      "PSR feature" ,"PSR feature"
      Link      "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      Link      "DTD Timings Table" , "DTD Timings"
      Link      "LFP PnP ID Table" , "LFP PnP ID"
      Link      "Backlight Control Parameters" , "Backlight Control Parameters"
      Link      "eDP Link Training Configuration Parameters" , "eDP Link Training Configuration Parameters"
      Link      "Chromaticity Control" , "Chromaticity Control"
      Link      "Apical Feature" , "Apical Feature"

      Page      "Panel Power Sequencing"
        Link      "Close Table", ".."

        Combo     $LcdVcc_On_During_S0_State_16, "Keep Panel Power enabled during S0 state: ", &No_Yes_List,
        Help      "This feature allows the panel power to be kept enabled during S0 state of the display.\r\n"
                  "When the user selects Yes, graphics driver will not disable Vcc when system is in S0 state.\r\n"
                  "When the user selects No, graphics driver will disable Vcc whenever panel is turned off. (In all Sx states).\r\n"
                  "Note: This option is only applicable for Windows Graphics driver."

        Combo     $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List,
        Help      "This feature enables or disables T3 optimization. \r\n"
                  "When enabled, VBIOS/GOP driver will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
                  "When disabled, VBIOS/GOP driver will wait for T3 time before trying the first AUX transaction"

        EditNum   $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", DEC,
        Help      "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 200msec\r\n"

        EditNum   $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Backlight Enable delay (T8):", DEC,
        Help      "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
                  "T8 is inclusive of T7.\r\n"
                  "Valid Range of T7: 0 to 50msec\r\n"

        EditNum   $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enable delay:", DEC,
        Help      "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
                  "Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
                  "So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

        EditNum   $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to PWM-Off delay:", DEC,
        Help      "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
                  "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
                  "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"

        EditNum   $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to End of Valid video data delay (T9):", DEC,
        Help      "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"

        EditNum   $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data to Power-Off delay (T10):", DEC,
        Help      "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
                  "Valid Range: 0 to 500 msec\r\n"

        EditNum   $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC,
        Help      "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage

      Page      "DTD Timings"
        Link      "Close Table" , ".."

        Table     $DVO_Tbl_16 " DTD Timings Values",
        Column    "Timings" , 1 byte , EHEX,
        Help      "This feature allows for the definition of the DTD timings parameters related to the LFP. "
                  "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                  "\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                  "\t    \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                  "\t    \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                  "\t    \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                  "\t    \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                  "\tByte14 \t: Vertical Image Size, LSB\r\n"
                  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                  "\t    \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                  "\tByte16 \t: Horizontal Border in pixels\r\n"
                  "\tByte17 \t: Vertical Border in lines\r\n"
                  "\tByte18 \t: Flags:\r\n"
                  "\t    \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                  "\t    \t:   Bit 6-5: 00 = Reserved\r\n"
                  "\t    \t:   Bit 4-3: 11 = Digital Separate\r\n"
                  "\t    \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                  "\t    \t:   Bit 0:   0 = Reserved"
      EndPage

      Page      "LFP PnP ID"
        Link      "Close Table" , ".."

        Table     $LVDS_PnP_ID_16 " LFP PnP ID Values",
        Column    "PnP ID" , 1 byte , EHEX,
        Help      "This feature allows the 10 bytes of EDID Vendor/Product ID "
                  "starting at offset 08h to be used as a PnP ID.\r\n\r\n"
                  " Table Definition:\r\n"
                  " \tWord:  ID Manufacturer Name\r\n"
                  " \tWord:  ID Product Code\r\n"
                  " \tDWord: ID Serial Number\r\n"
                  " \tByte:  Week of Manufacture\r\n"
                  " \tByte:  Year of Manufacture"
      EndPage

      Page      "Backlight Control Parameters"
        Link      "Close Table" , ".."

        Combo     $BLC_Inv_Type_16, "Inverter Type:", &Inv_Type_List,
        Help      "This feature allows for the selection of the Backlight Inverter type "
                  "that is to be used to control the backlight brightness of the LFP. \r\n"
                  "When PWM is selected, the driver and VBIOS will control the backlight brightness "
                  "via the integrated PWM solution for the applicable chipsets. \r\n"
                  "When None/External is selected, the system BIOS will control the backlight brightness "
                  "via the external solution."

        Combo     $Lfp_Pwm_Source_Selection_16, "  Pwm Source Selection:", &Pwm_Source_List,
        Help      "This field allows to select the Source of the PWM to be used  "
                  "for the selected Local Flat Panel.\r\n"

        Combo     $BLC_Inv_Polarity_16, "Inverter Polarity:", &Inv_Polarity_List,
        Help      "This feature allows the backlight inverter polarity to be specified.\r\n"
                  "Normal means 0 value is minimum brightness.\r\n"
                  "Inverted means 0 value is maximum brightness."

        EditNum   $BLC_Min_Brightness_16, "Minimum Brightness:", DEC,
        Help      "This feature allows defining the absolute minimum backlight brightness setting. "
                  "The graphics driver will never decrease the backlight less than this value. "
                  "The value must be specified using normal polarity semantics."

        EditNum   $POST_BL_Brightness_16, "POST Brightness:", DEC,
        Help      "This feature is used only by video BIOS to set initial brightness level at POST.\r\n"
                  "This is configurable field of 0-255. "
                  "Value of 0 indicates Zero brightness, 255 indicates maximum brightness."

        EditNum   $PWM_Frequency_16, "PWM Inverter Frequency (Hz):", DEC,
        Help      "This feature allows for the definition of the frequency needed for PWM Inverter.\r\n\r\n"
                  "Note: The frequency range (entered as a decimal number), for the integrated PWM is 200Hz - 40KHz."
      EndPage

      Page      "Chromaticity Control"
        Link      "Close Table" , ".."

        Combo     $Chromacity_Enable_16, "Chromaticity Control Feature", &Disabled_Enabled_List,
        Help      " This bit enables Chromaticity feature. \r\n"
                  " If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
                  " Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
                  " Please refer to section 3.7 of EDID Specification 1.4"

        Combo     $Override_EDID_Data_16, "Override the EDID values", &No_Yes_List,
        Help      "This option when enabled along with Chromaticity feature will override EDID values through following VBT data"

        EditNum   $Red_Green_16, "\tRed_Green_bits (Bits 1:0 at 19h)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"

        EditNum   $Blue_White_16, "\tBlue_White_bits (Bits 1:0 at 1Ah)" , EHEX,
        Help      " Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"

        EditNum   $Red_x_16, "\tRed_x (Bits 9:2 at 1Bh)" , EHEX,
        Help      " Bits 9:2 of red color x coordinate"

        EditNum   $Red_y_16, "\tRed_y (Bits 9:2 at 1Ch)" , EHEX,
        Help      " Bits 9:2 of red color y coordinate"

        EditNum   $Green_x_16, "\tGreen_x (Bits 9:2 at 1Dh)" , EHEX,
        Help      " Bits 9:2 of Green color x coordinate"

        EditNum   $Green_y_16, "\tGreen_y (Bits 9:2 at 1Eh)" , EHEX,
        Help      " Bits 9:2 of Green color y coordinate"

        EditNum   $Blue_x_16, "\tBlue_x (Bits 9:2 at 1F)" , EHEX,
        Help      " Bits 9:2 of Blue color x coordinate"

        EditNum   $Blue_y_16, "\tBlue_y (Bits 9:2 at 20h)" , EHEX,
        Help      " Bits 9:2 of Blue color y coordinate"

        EditNum   $White_x_16, "\tWhite_x (Bits 9:2 at 21h)" , EHEX,
        Help      " Bits 9:2 of White color x coordinate"

        EditNum   $White_y_16, "\tWhite_y (Bits 9:2 at 22h)" , EHEX,
        Help      " Bits 9:2 of White color y coordinate"
      EndPage   ; Chromaticity Control

      Page      "eDP Link Training Configuration Parameters"
        Link      "Close Table" , ".."

        TitleB    "Full Link Training Parameters"

        Combo     $eDP_Full_Link_Training_Params_Enable_16, "\tInitial Full link training parameters provided in VBT:", &No_Yes_List,
        Help      "This feature allows for the enable/disable of providing initial parameters for full link training."

        Combo     $eDP_Full_Link_Train_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Full_Link_Train_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Title     "  "

        TitleB    "Fast Link Training Parameters"

        Combo     $eDP_Fast_Link_Training_Supported_16, "\tIs FastLinkTraining Feature Supported:", &No_Yes_List,
        Help      "This feature allows for the selection of the Fast Link Training feature is to be enabled or disabled."

        Combo     $eDP_Link_DataRate_16, "\tData Rate:", &eDP_Link_DataRate_List,
        Help      "This feature allows for the selection of the Data Rate for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_LaneCount_16, "\tLane Count:", &eDP_Link_LaneCount_List,
        Help      "This feature allows for the selection of the Lane Count (Port Width) for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training."

        Combo     $eDP_Link_PreEmp_16, "\tPre-Emphasis:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of the Pre-emphasis value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Level-0, Level-1, Level-2 and Level-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."

        Combo     $eDP_Link_Vswing_16, "\tVoltage Swing:", &eDP_Link_VSwing_List,
        Help      "This feature allows for the selection of the Voltage Swing value for the embedded DP link. "
                  "It will be used if the sink indicates that no aux handshake is required during link training.\r\n"
                  "In case of Skylake/Kabylake, for Swing-0, Swing-1, Swing-2 and Swing-3 definitions: \r\n"
                  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \r\n"
                  "For Example: Panel #3 is configured for eDP. "
                  "Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'. "
                  "Based on selection refer to either default or Low Power VSwing/Pre-Emphasis table given in help text."
      EndPage

      Page      "PSR feature"
        Link      "Close Table" , ".."

        Combo     $PSR_FullLink_Enable_16, "Full Link enable:", &Yes_No_List,
        Help      "When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state."

        Combo     $PSR_Require_AUX2Wakeup_16, "Require AUX to wake up:", &Yes_No_List,
        Help      "When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used."

        Combo     $PSR_Lines2Wait_B4LinkS3_16, "Lines to wait before link standby:", &wait_line_link,
        Help      "This field determines Lines to wait before link standby \n"
                  " 0 lines to wait (Default)\r\n"
                  " 2 lines to wait\r\n"
                  " 4 lines to wait\r\n"
                  " 8 lines to wait\r\n"
                  " Others Reserved"

        EditNum   $PSR_IdleFrames2Wait_16, "Idle frames to wait:", DEC,
        Help      "Idle frames to wait for PSR enable.\n Allowed values 0-15. Default value is 0."

        Combo     $PSR_TP1_WaitTime_16, "TP1 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"

        Combo     $PSR_TP_2_3_WaitTime_16, "TP2/TP3 WakeUp Time:", &PsrWakeupTimeOptions,
        Help      "This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
      EndPage   ; PSR feature

      Page      "Apical Feature"
        Link      "Close Table" , ".."

        Combo     $eDP_Apical_Display_Ip_Enable_16, "Apical Assertive Display IP", &Disabled_Enabled_List,
        Help      "This field enables/disables the Apical Assertive Display IP for this panel."

        EditNum   $eDP_Panel_Oui_16, "\tPanel OUI (IEEE OUI)", EHEX,
        Help      "This field specifies the Apical IP specific Panel OUI field."

        EditNum   $eDP_Dpcd_Base_Address_16, "\tDPCD Base Address", EHEX,
        Help      "This field specifies the Apical IP specific DPCD base address field."

        EditNum   $eDP_Dpcd_Irdidix_Control0_16, "\tDPCD Irdidix Control 0", EHEX,
        Help      "This field specifies the Apical IP specific DPCD Irdidix control 0 field."

        EditNum   $eDP_Dpcd_Option_Select_16, "\tDPCD Option Select", EHEX,
        Help      "This field specifies the Apical IP specific DPCD option select field."

        EditNum   $eDP_Dpcd_Backlight_16, "\tDPCD Backlight", EHEX,
        Help      "This field specifies the Apical IP specific backlight value."

        EditNum   $eDP_Ambient_Light_16, "\tAmbient Light", EHEX,
        Help      "This field specifies the Apical IP specific Ambient light value."

        EditNum   $eDP_Backlight_Scale_16, "\tBacklight scale", EHEX,
        Help      "This field specifies the Apical IP specific backlight scale field."
      EndPage   ; Apical Feature
    EndPage   ; "Panel #16 "
  EndPage   ; "LFP Configuration"

  ;==============================================================================
  ; Page - Integrated DisplayPort/HDMI Configuration
  ;------------------------------------------------------------------------------

  Page      "Integrated DisplayPort/HDMI Configuration with External Connectors"
    Title     "Configurations for DisplayPort/HDMI Solution (External Connectors):"
    Link      "Close Window" , ".."

    Title     "DisplayPort SSC configuration: "
    Combo     $DP_SSC_Enb, "\tDisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List,
    Help      "This feature allow OEMs to enable/disable SSC for external DisplayPort. "
              "This feature is valid only the attached DisplayPort panel support SSC."

    Combo     $DP_SSC_Dongle_Enb, "\tDisplayPort Spread Spectrum Clock Enable/Disable for Dongles:", &Disabled_Enabled_List,
    Help      "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used "
              "and the attached DisplayPort panel should support SSC"

    Title     "DisplayPort Device Configuration "
    Link      "Device 1 Configuration" , "Device 1 (EFP1)"
    Link      "Device 2 Configuration" , "Device 2 (EFP2)"
    Link      "Device 3 Configuration" , "Device 3 (EFP3)"
    Link      "Device 4 Configuration" , "Device 4 (EFP4 for DDI-E only)"

    ;==============================================================================
    ; Page - Device 1 (EFP1)
    ;------------------------------------------------------------------------------
    Page      "Device 1 (EFP1)"
      Link      "Close Window" , ".."

      Combo     $Int_EFP1_Type, "Select Device Type:", &Int_EFP_Device_Type_List,
      Help      "This feature specifies the Device Type for this add-in device."

      Combo     $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List,
      Help      "This feature specifies which DVO port the device is configured."

      Combo     $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List,
      Help      "This feature specifies the GPIO pin pair used as DDC bus by this device. "
                "If this device doesn't support DDC bus, this field will be ignored."

      Combo     $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List,
      Help      "This feature specifies the AUX Channel for int-DisplayPort. "
                "This field is valid only if integrated DP is selected for Device Type."

      Combo     $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List,
      Help      "This feature specifies the Level shifter configuration for HDMI. "
                "This field is valid only if HDMI is selected for Device Type."

      Combo     $Int_EFP1_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List,
      Help      "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels"

      Combo     $Int_EFP1_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List,
      Help      "This field is applicable only if IBoost is enabled for the selected port."
                "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7"

      Combo     $Int_EFP1_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List,
      Help      "This field is applicable only if IBoost is enabled for the selected port."
                "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7"

      #IF       ($Embedded_Platform == 1)    ; Embedded platform
        Title     "    "

        Combo     $EFP1_EDIDless_en, "EDIDless Panel: ", &No_Yes_List,
        Help      "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority."

        Link      "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings"
      #ENDIF    ;  Embedded platform

      Title     "    "

      Combo     $LSPcon1_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions,
      Help      "This option is used to enable or disable the OnBoard LSPCON chip."

      Combo     $EFP1_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List,
      Help      "This feature, when enabled, will set lane reversal bit for selected Port "

      Combo     $EFP1_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List,
      Help      "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n"

      Combo     $Int_EFP1_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List,
      Help      "This feature will describe if this Port is Dockable or Not."

      Title     "Select DisplayPort Redriver "
      Link      "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )"

      Page      "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )"
        Combo     $Int_EFP1_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List,
        Help      "This feature will describe if Non-Dock Topology/OnBoard Redriver DP Link is present or Not."

        Combo     $Int_EFP1_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\r\n"
                  "Level 0 (0 dB)\n"
                  "Level 1 (3.5 dB)\n"
                  "Level 2 (6.0 dB)\n"
                  "Level 3 (9.5 dB)"

        Combo     $Int_EFP1_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List,
        Help      "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\r\n"
                  "Swing-0 (0.4 V)\n" 
                  "Swing-1 (0.6 V)\n"
                  "Swing-2 (0.8 V)\n"
                  ; "Swing-3 (1.2 V)"

        Title     "    "
        Combo     $Int_EFP1_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List,
        Help      "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not."

        Combo     $Int_EFP1_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n"
                  "Level 0 (0 dB)\n"
                  "Level 1 (3.5 dB)\n"
                  "Level 2 (6.0 dB)\n"
                  "Level 3 (9.5 dB)"

        Combo     $Int_EFP1_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List,
        Help      "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n"
                  "Swing-0 (0.4 V)\n" 
                  "Swing-1 (0.6 V)\n"
                  "Swing-2 (0.8 V)\n"
                  ; "Swing-3 (1.2 V)"
      EndPage   ; "DisplayPort Redriver Configuration"

      #IF       ($Embedded_Platform == 1)    ; Embedded platform
        Page      "EDID-less EFP Panel DTD Timings"
          Link      "Close Table" , ".."

          Table     $EFP1_DTD " DTD Timings Values",
          Column    "Timings" , 1 byte , EHEX,
          Help      "This feature allows for the definition of the DTD timings parameters. "
                    "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                    "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                    "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                    "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                    "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                    "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                    "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                    "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                    "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                    "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                    "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                    "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                    "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                    "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                    "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                    "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                    "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                    "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                    "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                    "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                    "\tByte14 \t: Vertical Image Size, LSB\r\n"
                    "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                    "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                    "\tByte16 \t: Horizontal Border in pixels\r\n"
                    "\tByte17 \t: Vertical Border in lines\r\n"
                    "\tByte18 \t: Flags:\r\n"
                    "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                    "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
                    "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
                    "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                    "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                    "\t   \t:   Bit 0:   0 = Reserved"
        EndPage   ; "EDID-less EFP Panel DTD Timings"
      #ENDIF    ; Embedded platform
    EndPage   ; "Device 1 (EFP1)"

    ;==============================================================================
    ; Page - Device 2 (EFP2)
    ;------------------------------------------------------------------------------
    Page      "Device 2 (EFP2)"
      Link      "Close Window" , ".."

      Combo     $Int_EFP2_Type, "Select Device Type:", &Int_EFP_Device_Type_List,
      Help      "This feature specifies the Device Type for this add-in device."

      Combo     $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List,
      Help      "This feature specifies which DVO port the device is configured."

      Combo     $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List,
      Help      "This feature specifies the GPIO pin pair used as DDC bus by this device. "
                "If this device doesn't support DDC bus, this field will be ignored."

      Combo     $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List,
      Help      "This feature specifies the AUX Channel for int-DisplayPort. "
                "This field is valid only if integrated DP is selected for Device Type."

      Combo     $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List,
      Help      "This feature specifies the Level shifter configuration for HDMI. "
                "This field is valid only if HDMI is selected for Device Type."

      Combo     $Int_EFP2_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List,
      Help      "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels"

      Combo     $Int_EFP2_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List,
      Help      "This field is applicable only if IBoost is enabled for the selected port."
                "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7"

      Combo     $Int_EFP2_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List,
      Help      "This field is applicable only if IBoost is enabled for the selected port."
                "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7"

      #IF       ($Embedded_Platform == 1)    ; Embedded platform
        Title     "    "

        Combo     $EFP2_EDIDless_en, "EDIDless Panel: ", &No_Yes_List,
        Help      "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority."

        Link      "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings"
      #ENDIF    ; Embedded platform

      Title     "    "

      Combo     $LSPcon2_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions,
      Help      "This option is used to enable or disable the OnBoard LSPCON chip."

      Combo     $EFP2_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List,
      Help      "This feature, when enabled, will set lane reversal bit for selected Port "

      Combo     $EFP2_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List,
      Help      "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n"

      Combo     $Int_EFP2_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List,
      Help      "This feature will describe if this port is dockable or not."

      Title     "Select DisplayPort Redriver "
      Link      "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )"

      Page      "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )"
        Combo     $Int_EFP2_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List,
        Help      "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not."

        Combo     $Int_EFP2_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n"
                  "Level 0 (0 dB)\n"
                  "Level 1 (3.5 dB)\n"
                  "Level 2 (6.0 dB)\n"
                  "Level 3 (9.5 dB)"

        Combo     $Int_EFP2_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List,
        Help      "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n"
                  "Swing-0 (0.4 V)\n" 
                  "Swing-1 (0.6 V)\n"
                  "Swing-2 (0.8 V)\n"
                  ; "Swing-3 (1.2 V)"

        Title     "    "
        Combo     $Int_EFP2_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List,
        Help      "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n"

        Combo     $Int_EFP2_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link.\r\n"
                  "Level 0 (0 dB)\n"
                  "Level 1 (3.5 dB)\n"
                  "Level 2 (6.0 dB)\n"
                  "Level 3 (9.5 dB)"

        Combo     $Int_EFP2_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List,
        Help      "This feature allows for the selection of voltage swing level for the Dock redriver DP link."
                  "Swing-0 (0.4 V)\n" 
                  "Swing-1 (0.6 V)\n"
                  "Swing-2 (0.8 V)\n"
                  ; "Swing-3 (1.2 V)"
      EndPage   ; "DisplayPort Redriver Configuration"

      #IF       ($Embedded_Platform == 1)    ; Embedded platform
        Page      "EDID-less EFP Panel DTD Timings"
          Link      "Close Table" , ".."

          Table     $EFP2_DTD " DTD Timings Values",
          Column    "Timings" , 1 byte , EHEX,
          Help      "This feature allows for the definition of the DTD timings parameters. "
                    "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                    "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                    "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                    "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                    "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                    "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                    "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                    "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                    "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                    "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                    "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                    "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                    "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                    "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                    "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                    "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                    "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                    "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                    "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                    "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                    "\tByte14 \t: Vertical Image Size, LSB\r\n"
                    "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                    "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                    "\tByte16 \t: Horizontal Border in pixels\r\n"
                    "\tByte17 \t: Vertical Border in lines\r\n"
                    "\tByte18 \t: Flags:\r\n"
                    "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                    "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
                    "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
                    "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                    "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                    "\t   \t:   Bit 0:   0 = Reserved"
        EndPage   ; "EDID-less EFP Panel DTD Timings"
      #ENDIF    ; Embedded platform
    EndPage   ; "Device 2"  (EFP2)

    ;==============================================================================
    ; Page - Device 3 (EFP3)
    ;------------------------------------------------------------------------------
    Page      "Device 3 (EFP3)"
      Link      "Close Window" , ".."

      Combo     $Int_EFP3_Type, "Select Device Type:", &Int_EFP_Device_Type_List,
      Help      "This feature specifies the Device Type for this add-in device."

      Combo     $Int_EFP3_Port, "Select Output Port:", &Int_EFP_Port_List,
      Help      "This feature specifies which DVO port the device is configured."

      Combo     $Int_EFP3_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List,
      Help      "This feature specifies the GPIO pin pair used as DDC bus by this device. "
                "If this device doesn't support DDC bus, this field will be ignored."

      Combo     $Int_EFP3_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List,
      Help      "This feature specifies the AUX Channel for int-DisplayPort. "
                "This field is valid only if integrated DP is selected for Device Type."

      Combo     $Int_EFP3_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_LS_List,
      Help      "This feature specifies the Level shifter configuration for HDMI. "
                "This field is valid only if HDMI is selected for Device Type."

      Combo     $Int_EFP3_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List,
      Help      "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels"

      Combo     $Int_EFP3_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List,
      Help      "This field is applicable only if IBoost is enabled for the selected port."
                "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7"

      Combo     $Int_EFP3_Hdmi_Boost_Magnitude, "\tIBoost Magnitude for HDMI display: ", &IBoost_Magnitude_List,
      Help      "This field is applicable only if IBoost is enabled for the selected port."
                "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7"

      #IF       ($Embedded_Platform == 1)    ; Embedded platform
        Title     "    "

        Combo     $EFP3_EDIDless_en, "EDIDless Panel: ", &No_Yes_List,
        Help      "If the Attached panel is EDIDless select Yes and the supplied DTD takes priority."

        Link      "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings"
      #ENDIF    ; Embedded platform

      Title     "    "

      Combo     $LSPcon3_Options, "OnBoard LSPCON for HDMI 2.0: ", &Hdmi2SupportOptions,
      Help      "This option is used to enable or disable the OnBoard LSPCON chip."

      Combo     $EFP3_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List,
      Help      "This feature, when enabled, will set lane reversal bit for selected Port "

      Combo     $EFP3_USB_C_DongleFeature_Enabled, "USB-Type-C Dongle Feature Enabled:", &Disabled_Enabled_List,
      Help      "This option Enables/Disables USB-Type-C Dongle Feature for USB Type C port for DP panels.\r\n"

      Combo     $Int_EFP3_Port_Dockable, "Dockable Port: (Mobile only)", &No_Yes_List,
      Help      "This feature will describe if this Port is Dockable or Not."

      Title     "Select DisplayPort Redriver "
      Link      "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )" , "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )"

      Page      "Select DisplayPort Redriver Configuration ( Dock/ OnBoard )"
        Combo     $Int_EFP3_OnBoard_Redriver_Present, "Non-dock topology: (OnBoard)", &No_Yes_List,
        Help      "This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not."

        Combo     $Int_EFP3_OnBoard_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of Pre-emphasis level for the OnBoard redriver DP link.\n"
                  "Level 0 (0 dB)\n"
                  "Level 1 (3.5 dB)\n"
                  "Level 2 (6.0 dB)\n"
                  "Level 3 (9.5 dB)"

        Combo     $Int_EFP3_OnBoard_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List,
        Help      "This feature allows for the selection of voltage swing level for the OnBoard redriver DP link.\n"
                  "Swing-0 (0.4 V)\n" 
                  "Swing-1 (0.6 V)\n"
                  "Swing-2 (0.8 V)\n"
                  ; "Swing-3 (1.2 V)"

        Title     "    "
        Combo     $Int_EFP3_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List,
        Help      "This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n"

        Combo     $Int_EFP3_Dock_Pre_emphasis, "\tPre-Emphasis Level:", &DP_eDP_Link_PreEmp_List,
        Help      "This feature allows for the selection of Pre-emphasis level for the Dock redriver DP link."
                  "Level 0 (0 dB)\n"
                  "Level 1 (3.5 dB)\n"
                  "Level 2 (6.0 dB)\n"
                  "Level 3 (9.5 dB)"

        Combo     $Int_EFP3_Dock_Voltage_swing, "\tVoltage Swing Level:", &DP_Link_VSwing_List,
        Help      "This feature allows for the selection of voltage swing level for the Dock redriver DP link.\r\n"
                  "Swing-0 (0.4 V)\n" 
                  "Swing-1 (0.6 V)\n"
                  "Swing-2 (0.8 V)\n"
                  ; "Swing-3 (1.2 V)"
      EndPage   ; "DisplayPort Redriver Configuration"

      #IF       ($Embedded_Platform == 1)    ; Embedded platform
        Page      "EDID-less EFP Panel DTD Timings"
          Link      "Close Table" , ".."

          Table     $EFP3_DTD " DTD Timings Values",
          Column    "Timings" , 1 byte , EHEX,
          Help      "This feature allows for the definition of the DTD timings parameters. "
                    "The table is the 18-byte DTD structure defined in the VESA EDID version 1.x.\r\n\r\n"
                    "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                    "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                    "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                    "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                    "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                    "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                    "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                    "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                    "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                    "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                    "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                    "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                    "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                    "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                    "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                    "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                    "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                    "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                    "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                    "\tByte14 \t: Vertical Image Size, LSB\r\n"
                    "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                    "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                    "\tByte16 \t: Horizontal Border in pixels\r\n"
                    "\tByte17 \t: Vertical Border in lines\r\n"
                    "\tByte18 \t: Flags:\r\n"
                    "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                    "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
                    "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
                    "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                    "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                    "\t   \t:   Bit 0:   0 = Reserved"
        EndPage   ; "EDID-less EFP Panel DTD Timings"
      #ENDIF    ; Embedded platform
    EndPage   ; "Device 3  (EFP3)"

    ;==============================================================================
    ; Page - Device 4 (EFP4)
    ;------------------------------------------------------------------------------
    Page      "Device 4 (EFP4 for DDI-E only)"
      Link      "Close Window" , ".."

      Combo     $Int_EFP4_Type, "Select Device Type:", &Int_EFP4_Device_Type_List,
      Help      "This feature specifies the Device Type for this add-in device."

      Combo     $Int_EFP4_Port, "Select Output Port:", &Int_EFP4_Port_List,
      Help      "This feature specifies which DVO port the device is configured."

      Combo     $Int_EFP4_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List,
      Help      "This feature specifies the AUX Channel for int-DisplayPort. "
                "This field is valid only if integrated DP is selected for Device Type."

      Combo     $Int_EFP4_IBoost_Enable, "IBoost Feature: ", &Disabled_Enabled_List,
      Help      "This feature, when enabled, will enable the IBoost for Selected Port on all the VSwing/Pre-Emphasis levels"

      Combo     $Int_EFP4_Dp_Boost_Magnitude, "\tIBoost Magnitude for DP display: ", &IBoost_Magnitude_List,
      Help      "This field is applicable only if IBoost is enabled for the selected port."
                "The IBoost magnitude levels supported on SKL/KBL are 0x1, 0x3, 0x7"

    EndPage   ; "Device 4 (EFP4)"

  EndPage   ; "Integrated DisplayPort/HDMI Configuration with External Connectors"
EndPage   ; Display configuration

;==============================================================================
; Page - Display Device Toggle Lists
;------------------------------------------------------------------------------
Page      "Display Device Toggle Lists (Mobile only)"
  Link      "Toggle/Capabilities List 1" , "Display Toggle List 1"
  Link      "Toggle/Capabilities List 2" , "Display Toggle List 2"
  Link      "Toggle/Capabilities List 3" , "Display Toggle List 3"
  Link      "Toggle/Capabilities List 4" , "Display Toggle List 4"

  Page      "Display Toggle List 1"
    Link      "Close Table" , ".."

    Table     $Toggle_List1 "Display Toggle List 1",
    Column    "Display Select", 2 bytes, EHEX,

    Help      "These toggle lists are used by the video BIOS and Graphics drivers "
              "to help support the system BIOS with switch display device Hot Keys. "
              "The basic algorithm is that the current display is found on the list and "
              "the next settable display combination is set. "
              "If no settable display combinations are found the function returns fail.\r\n\r\n"
              "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n"
              "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
              "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n"
              "EFPx.x nomenclature\r\n"
              "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
              "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
              "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
              "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n"
              "Examples:\r\n"
              "\t Display Config\r\n"
              "\t00000000 00001100b  ; Toggle display to EFP & LFP combination\r\n"
              "\t00000100 00001000b  ; Toggle display to second DP Port on EFP3 and LFP combination."
  EndPage   ; Display Toggle List 1

  Page      "Display Toggle List 2"
    Link      "Close Table" , ".."

    Table     $Toggle_List2 "Display Toggle List 2",
    Column    "Display Select", 2 bytes, EHEX,
    Help      "These toggle lists are used by the video BIOS and Graphics drivers "
              "to help support the system BIOS with switch display device Hot Keys. "
              "The basic algorithm is that the current display is found on the list and "
              "the next settable display combination is set. "
              "If no settable display combinations are found the function returns fail.\r\n\r\n"
              "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n"
              "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
              "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n"
              "EFPx.x nomenclature\r\n"
              "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
              "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
              "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
              "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n"
              "Examples:\r\n"
              "\t Display Config\r\n"
              "\t00000000 00001100b  ; Toggle display to EFP & LFP combination\r\n"
              "\t00000100 00001000b  ; Toggle display to second DP Port on EFP3 and LFP combination."
  EndPage   ; Display Toggle List 2

  Page      "Display Toggle List 3"
    Link      "Close Table" , ".."

    Table     $Toggle_List3 "Display Toggle List 3",
    Column    "Display Select", 2 bytes, EHEX,
    Help      "These toggle lists are used by the video BIOS and Graphics drivers "
              "to help support the system BIOS with switch display device Hot Keys. "
              "The basic algorithm is that the current display is found on the list and "
              "the next settable display combination is set. "
              "If no settable display combinations are found the function returns fail.\r\n\r\n"
              "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n"
              "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
              "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n"
              "EFPx.x nomenclature\r\n"
              "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
              "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
              "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
              "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n"
              "Examples:\r\n"
              "\t Display Config\r\n"
              "\t00000000 00001100b  ; Toggle display to EFP & LFP combination\r\n"
              "\t00000100 00001000b  ; Toggle display to second DP Port on EFP3 and LFP combination."
  EndPage   ; Display Toggle List 3

  Page      "Display Toggle List 4"
    Link      "Close Table" , ".."

    Table     $Toggle_List4 "Display Toggle List 4",
    Column    "Display Select", 2 bytes, EHEX,
    Help      "These toggle lists are used by the video BIOS and Graphics drivers "
              "to help support the system BIOS with switch display device Hot Keys. "
              "The basic algorithm is that the current display is found on the list and "
              "the next settable display combination is set. "
              "If no settable display combinations are found the function returns fail.\r\n\r\n"
              "Four lists are given to allow for multiple Hot Keys or creative solutions.\r\n\r\n"
              "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
              "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n"
              "EFPx.x nomenclature\r\n"
              "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
              "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
              "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
              "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n"
              "Examples:\r\n"
              "\t Display Config\r\n"
              "\t00000000 00001100b  ; Toggle display to EFP & LFP combination\r\n"
              "\t00000100 00001000b  ; Toggle display to second DP Port on EFP3 and LFP combination."
  EndPage   ; Display Toggle List 4
EndPage   ; Display Device Toggle Lists

;==============================================================================
; Page - Modes Removal Table
;------------------------------------------------------------------------------

Page      "Modes Removal Table"

  Table     $Mode_Rem_Table "Modes Removal Table",
  Column    "X-Resolution",     2 bytes, DEC
  Column    "Y-Resolution",     2 bytes, DEC
  Column    "BPP",              1 byte,  DEC
  Column    "Refresh Rate",     2 bytes, EHEX
  Column    "Removal Flags",    1 byte,  EHEX
  Column    "Panel Type",       2 bytes, EHEX,

  Help      "This feature allows removing support for selected modes resolutions.\r\n"
            "X-Resolution, Y-Resolution, and BPP in Decimal or Hexadecimal (0FFFFh or 0FFh means disable all).\r\n\r\n"
            "Refresh Rate bitmap selection (0 = Do not remove, 1 = Remove):\r\n"
            "\tBit \t  15-14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 \r\n"
            "\tRRate(Hz)  Rsvd \t25 \t24 \t50 \t40 \t30 \t120 \t100 \t85 \t75 \t72 \t70 \t60 \t56 \t43 \r\n\r\n"
            "Removal Flags bitmap selection (0 = Do not remove, 1 = Remove):\r\n"
            "\tBit        \t     7 \t  6 \t\t5 \t4 \t3 \t2 \t1 \t0 \r\n"
            "\tComponent  Rsvd \tTV Scan Mode \tLFP \tEFP \tRsvd \tRsvd \tDriver \tRsvd \r\n\r\n"
            "Note: \t1) In order to remove mode from both Windows and DOS, "
            "both bits 1 and Bit 0 must be set to 1.\r\n"
            "\t2) The defaule setting '0' for Bit6 is for removing Progressive scan mode from TV device, "
            "and setting '1' is for removing Interlaced scan mode from TV device.\r\n\r\n"
            "(Mobile only) Panel Type bitmap selection (0 = Do not remove, 1 = Remove if panel is active):\r\n"
            "\tBit  \t15 14 13 12 11 10  9  8 7 6 5 4 3 2 1 0 \r\n"
            "\tType \t16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n"
            "Note: Default is to remove a mode resolution from all panel types."
EndPage

;==============================================================================
; Page - Display Configuration Removal Table
;------------------------------------------------------------------------------
Page      "Display Configuration Removal Table (Mobile only)"

  Table     $Dev_Removed_Table " Display Device Configuration Removal Table",
  Column    "Display Configuration" , 2 bytes , EHEX,
  Help      "This feature allows blocking selected display configurations by the driver.\r\n"
            "Display Devices are specified in the following bit patterns:\r\n"
            "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
            "\tEFP4.3\tEFP3.3\tEFP2.3\tEFP1.3\tEFP4.2\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd\r\n\r\n"
            "EFPx.x nomenclature\r\n"
            "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
            "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
            "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
            "EFP4.3 - 3rd daisy chained DP port on EFP4 Port\r\n"
            "Examples:\r\n"
            "\tDisplay Config\r\n"
            "\t00000000 00001100b  ; EFP & LFP combination to be removed\r\n"
            "\t00000100 00001000b  ; Second DP Port on EFP3 and LFP to be removed."
EndPage

;==============================================================================
; Page - OEM Customizable Modes
;------------------------------------------------------------------------------
Page      "OEM Customizable Modes"
  Link      "OEM Mode 1 Configuration", "OEM Mode #1"
  Link      "OEM Mode 2 Configuration", "OEM Mode #2"
  Link      "OEM Mode 3 Configuration", "OEM Mode #3"
  Link      "OEM Mode 4 Configuration", "OEM Mode #4"
  Link      "OEM Mode 5 Configuration", "OEM Mode #5"
  Link      "OEM Mode 6 Configuration", "OEM Mode #6"

  Page      "OEM Mode #1"
    Link      "Close Table" , ".."

    Title     "     8 bpp = VGA mode 60h / VESA mode 160h"
    Title     "    16 bpp = VGA mode 61h / VESA mode 161h"
    Title     "    32 bpp = VGA mode 62h / VESA mode 162h"

    EditNum   $OEM_Mode_Flags1, "Support Flags:", BIN,
    Help      "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tDriver\tRsvd"

    EditNum   $OEM_Display_Flags1, "Display Flags:", BIN,
    Help      "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
              "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd"

    TitleB    "Mode Characteristics"
    EditNum   $OEM_Mode_X1, "\tX Resolution:", DEC,
    Help      "X Resolution in pixels (decimal)."

    EditNum   $OEM_Mode_Y1, "\tY Resolution:", DEC,
    Help      "Y Resolution in pixels (decimal)."

    EditNum   $OEM_Mode_Color1, "\tColor Depth:", BIN,
    Help      "Color Depth, bits can be set simultaneously (binary).\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t  Bit 0\r\n"
              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP"

    EditNum   $OEM_Mode_RRate1, "\tRefresh Rate:", DEC,
    Help      "Refresh rate for OEM customizable mode (decimal)."
    Link      "18 Bytes DTD" , "DTD"

    Page      "DTD"
      Link      "Close Table" , ".."
      Table     $OEM_Mode_DTD1 " Detailed Timings Descriptor",
      Column    "Timings" , 1 byte , EHEX,
      Help      "This table is the 18-byte DTD(Detailed Timings Descriptor) structure "
                "as defined in the VESA EDID version 1.x. "
                "This is used by VBIOS only.\r\n\r\n"
                "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                "\tByte14 \t: Vertical Image Size, LSB\r\n"
                "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                "\tByte16 \t: Horizontal Border in pixels\r\n"
                "\tByte17 \t: Vertical Border in lines\r\n"
                "\tByte18 \t: Flags:\r\n"
                "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
                "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
                "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                "\t   \t:   Bit 0:   0 = Reserved"
    EndPage   ; DTD
  EndPage   ; OEM Mode #1

  Page      "OEM Mode #2"
    Link      "Close Table" , ".."

    Title     "     8 bpp = VGA mode 63h / VESA mode 163h"
    Title     "    16 bpp = VGA mode 64h / VESA mode 164h"
    Title     "    32 bpp = VGA mode 65h / VESA mode 165h"

    EditNum   $OEM_Mode_Flags2, "Support Flags:", BIN,
    Help      "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tDriver\tRsvd"

    EditNum   $OEM_Display_Flags2, "Display Flags:", BIN,
    Help      "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
              "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd"

    TitleB    "Mode Characteristics"

    EditNum   $OEM_Mode_X2, "\tX Resolution:", DEC,
    Help      "X Resolution in pixels (decimal)."

    EditNum   $OEM_Mode_Y2, "\tY Resolution:", DEC,
    Help      "Y Resolution in pixels (decimal)."

    EditNum   $OEM_Mode_Color2, "\tColor Depth:", BIN,
    Help      "Color Depth, bits can be set simultaneously (binary).\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t  Bit 0\r\n"
              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP"

    EditNum   $OEM_Mode_RRate2, "\tRefresh Rate:", DEC,
    Help      "Refresh rate for OEM customizable mode (decimal)."

    Link      "18 Bytes DTD" , "DTD"

    Page      "DTD"
      Link      "Close Table" , ".."

      Table     $OEM_Mode_DTD2 " Detailed Timings Descriptor",
      Column    "Timings" , 1 byte , EHEX,
      Help      "This table is the 18-byte DTD(Detailed Timings Descriptor) structure "
                "as defined in the VESA EDID version 1.x. "
                "This is used by VBIOS only.\r\n\r\n"
                "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                "\tByte14 \t: Vertical Image Size, LSB\r\n"
                "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                "\tByte16 \t: Horizontal Border in pixels\r\n"
                "\tByte17 \t: Vertical Border in lines\r\n"
                "\tByte18 \t: Flags:\r\n"
                "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
                "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
                "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                "\t   \t:   Bit 0:   0 = Reserved"
    EndPage   ; DTD
  EndPage   ; OEM Mode #2

  Page      "OEM Mode #3"
    Link      "Close Table" , ".."

    Title     "     8 bpp = VGA mode 66h / VESA mode 166h"
    Title     "    16 bpp = VGA mode 67h / VESA mode 167h"
    Title     "    32 bpp = VGA mode 68h / VESA mode 168h"

    EditNum   $OEM_Mode_Flags3, "Support Flags:", BIN,
    Help      "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tDriver\tRsvd"

    EditNum   $OEM_Display_Flags3, "Display Flags:", BIN,
    Help      "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
              "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd"

    TitleB    "Mode Characteristics"

    EditNum   $OEM_Mode_X3, "\tX Resolution:", DEC,
    Help      "X Resolution in pixels (decimal)."

    EditNum   $OEM_Mode_Y3, "\tY Resolution:", DEC,
    Help      "Y Resolution in pixels (decimal)."

    EditNum   $OEM_Mode_Color3, "\tColor Depth:", BIN,
    Help      "Color Depth, bits can be set simultaneously (binary).\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t  Bit 0\r\n"
              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP"

    EditNum   $OEM_Mode_RRate3, "\tRefresh Rate:", DEC,
    Help      "Refresh rate for OEM customizable mode (decimal)."

    Link      "18 Bytes DTD" , "DTD"

    Page      "DTD"
      Link      "Close Table" , ".."

      Table     $OEM_Mode_DTD3 " Detailed Timings Descriptor",
      Column    "Timings" , 1 byte , EHEX,
      Help      "This table is the 18-byte DTD(Detailed Timings Descriptor) structure "
                "as defined in the VESA EDID version 1.x. "
                "This is used by VBIOS only.\r\n\r\n"
                "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                "\tByte14 \t: Vertical Image Size, LSB\r\n"
                "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                "\tByte16 \t: Horizontal Border in pixels\r\n"
                "\tByte17 \t: Vertical Border in lines\r\n"
                "\tByte18 \t: Flags:\r\n"
                "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
                "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
                "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                "\t   \t:   Bit 0:   0 = Reserved"
    EndPage   ; DTD
  EndPage   ; OEM Mode #3

  Page      "OEM Mode #4"
    Link      "Close Table" , ".."

    Title     "     8 bpp = VGA mode 69h / VESA mode 169h"
    Title     "    16 bpp = VGA mode 6Ah / VESA mode 16Ah"
    Title     "    32 bpp = VGA mode 6Bh / VESA mode 16Bh"

    EditNum   $OEM_Mode_Flags4, "Support Flags:", BIN,
    Help      "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tDriver\tRsvd"

    EditNum   $OEM_Display_Flags4, "Display Flags:", BIN,
    Help      "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
              "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd"

    TitleB    "Mode Characteristics"

    EditNum   $OEM_Mode_X4, "\tX Resolution:", DEC,
    Help      "X Resolution in pixels (decimal)."

    EditNum   $OEM_Mode_Y4, "\tY Resolution:", DEC,
    Help      "Y Resolution in pixels (decimal)."

    EditNum   $OEM_Mode_Color4, "\tColor Depth:", BIN,
    Help      "Color Depth, bits can be set simultaneously (binary).\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t  Bit 0\r\n"
              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP"

    EditNum   $OEM_Mode_RRate4, "\tRefresh Rate:", DEC,
    Help      "Refresh rate for OEM customizable mode (decimal)."

    Link      "18 Bytes DTD" , "DTD"

    Page      "DTD"

      Link      "Close Table" , ".."

      Table     $OEM_Mode_DTD4 " Detailed Timings Descriptor",
      Column    "Timings" , 1 byte , EHEX,
      Help      "This table is the 18-byte DTD(Detailed Timings Descriptor) structure "
                "as defined in the VESA EDID version 1.x. "
                "This is used by VBIOS only.\r\n\r\n"
                "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                "\tByte14 \t: Vertical Image Size, LSB\r\n"
                "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                "\tByte16 \t: Horizontal Border in pixels\r\n"
                "\tByte17 \t: Vertical Border in lines\r\n"
                "\tByte18 \t: Flags:\r\n"
                "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
                "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
                "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                "\t   \t:   Bit 0:   0 = Reserved"
    EndPage   ; DTD
  EndPage   ; OEM Mode #4

  Page      "OEM Mode #5"
    Link      "Close Table" , ".."

    Title     "     8 bpp = VGA mode 6Ch / VESA mode 16Ch"
    Title     "    16 bpp = VGA mode 6Dh / VESA mode 16Dh"
    Title     "    32 bpp = VGA mode 6Eh / VESA mode 16Eh"

    EditNum   $OEM_Mode_Flags5, "Support Flags:", BIN,
    Help      "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tDriver\tRsvd"

    EditNum   $OEM_Display_Flags5, "Display Flags:", BIN,
    Help      "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
              "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd"

    TitleB    "Mode Characteristics"

    EditNum   $OEM_Mode_X5, "\tX Resolution:", DEC,
    Help      "X Resolution in pixels (decimal)."

    EditNum   $OEM_Mode_Y5, "\tY Resolution:", DEC,
    Help      "Y Resolution in pixels (decimal)."

    EditNum   $OEM_Mode_Color5, "\tColor Depth:", BIN,
    Help      "Color Depth, bits can be set simultaneously (binary).\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t  Bit 0\r\n"
              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP"

    EditNum   $OEM_Mode_RRate5, "\tRefresh Rate:", DEC,
    Help      "Refresh rate for OEM customizable mode (decimal)."

    Link      "18 Bytes DTD" , "DTD"

    Page      "DTD"
      Link      "Close Table" , ".."

      Table     $OEM_Mode_DTD5 " Detailed Timings Descriptor",
      Column    "Timings" , 1 byte , EHEX,
      Help      "This table is the 18-byte DTD(Detailed Timings Descriptor) structure "
                "as defined in the VESA EDID version 1.x. "
                "This is used by VBIOS only.\r\n\r\n"
                "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                "\tByte14 \t: Vertical Image Size, LSB\r\n"
                "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                "\tByte16 \t: Horizontal Border in pixels\r\n"
                "\tByte17 \t: Vertical Border in lines\r\n"
                "\tByte18 \t: Flags:\r\n"
                "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
                "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
                "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                "\t   \t:   Bit 0:   0 = Reserved"
    EndPage   ; DTD
  EndPage   ; OEM Mode #5

  Page      "OEM Mode #6"
    Link      "Close Table" , ".."

    Title     "     8 bpp = VGA mode 6Fh / VESA mode 16Fh"
    Title     "    16 bpp = VGA mode 70h / VESA mode 170h"
    Title     "    32 bpp = VGA mode 71h / VESA mode 171h"

    EditNum   $OEM_Mode_Flags6, "Support Flags:", BIN,
    Help      "Support flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\tDriver\tRsvd"

    EditNum   $OEM_Display_Flags6, "Display Flags:", BIN,
    Help      "Display Flags: (0 = Disabled, 1 = Enabled)\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\tBit 0\r\n"
              "\tLFP2\tEFP2\tEFP3\tEFP4\tLFP\tEFP\tRsvd\tRsvd"

    TitleB    "Mode Characteristics"

    EditNum   $OEM_Mode_X6, "\tX Resolution:", DEC,
    Help      "X Resolution in pixels (decimal)."

    EditNum   $OEM_Mode_Y6, "\tY Resolution:", DEC,
    Help      "Y Resolution in pixels (decimal)."

    EditNum   $OEM_Mode_Color6, "\tColor Depth:", BIN,
    Help      "Color Depth, bits can be set simultaneously (binary).\r\n\r\n"
              "\tBit 7\tBit 6\tBit 5\tBit 4\tBit 3\tBit 2\tBit 1\t  Bit 0\r\n"
              "\tRsvd\tRsvd\tRsvd\tRsvd\tRsvd\t32 BPP\t16 BPP\t8 BPP"

    EditNum   $OEM_Mode_RRate6, "\tRefresh Rate:", DEC,
    Help      "Refresh rate for OEM customizable mode (decimal)."

    Link      "18 Bytes DTD" , "DTD"

    Page      "DTD"
      Link      "Close Table" , ".."

      Table     $OEM_Mode_DTD6 " Detailed Timings Descriptor",
      Column    "Timings" , 1 byte , EHEX,
      Help      "This table is the 18-byte DTD(Detailed Timings Descriptor) structure "
                "as defined in the VESA EDID version 1.x. "
                "This is used by VBIOS only.\r\n\r\n"
                "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
                "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
                "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
                "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
                "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
                "\tByte6 \t: Vertical Active in lines, LSB\r\n"
                "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
                "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
                "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
                "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
                "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
                "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
                "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
                "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
                "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
                "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
                "\tByte13 \t: Horizontal Image Size, LSB\r\n"
                "\tByte14 \t: Vertical Image Size, LSB\r\n"
                "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
                "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
                "\tByte16 \t: Horizontal Border in pixels\r\n"
                "\tByte17 \t: Vertical Border in lines\r\n"
                "\tByte18 \t: Flags:\r\n"
                "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
                "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
                "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
                "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
                "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
                "\t   \t:   Bit 0:   0 = Reserved"
    EndPage   ; DTD
  EndPage   ; OEM Mode #6
EndPage   ; OEM Customizable Modes
;============================================================================
; End of File
;----------------------------------------------------------------------------
